You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
"displayName": "Getting Started with Multiple Configurations for the Configurable Logic Block (CLB) - Use Case for the PIC16F13145 Microcontroller with MCC Melody",
"shortDescription": "This repository provides an MPLAB X project highlighting how different bitstream configurations for the Configurable Logic Block (CLB) peripheral can be changed and loaded at runtime.",
"displayName": "Getting Started with Multiple Configurations for the Configurable Logic Block (CLB) - Use Case for the PIC16F13145 Microcontroller with MCC Melody",
"shortDescription": "This repository provides an MPLAB X project highlighting how different bitstream configurations for the Configurable Logic Block (CLB) peripheral can be changed and loaded at runtime.",
Copy file name to clipboardExpand all lines: README.md
+32-33Lines changed: 32 additions & 33 deletions
Display the source diff
Display the rich diff
Original file line number
Diff line number
Diff line change
@@ -6,7 +6,7 @@
6
6
</picture>
7
7
</a>
8
8
9
-
# Getting Started With Multiple Configurations for the Configurable Logic Block (CLB) – Use Case for the PIC16F13145 Microcontroller With MCC Melody
9
+
# Getting Started With Multiple Configurations for the Configurable Logic Block (CLB) – Use Case for the PIC16F13145 Microcontroller with MCC Melody
10
10
11
11
The PIC16F13145 device family of microcontrollers is equipped with a Configurable Logic Block (CLB) peripheral. The CLB is a collection of logic elements that can be programmed to perform a wide variety of digital logic functions. The logic function may be completely combinatorial, sequential or a combination of the two, enabling users to incorporate hardware-based custom logic into their applications. This peripheral presents a unique way of modifying its control registers and setting up the logic elements. The CLB module consists of two sets of register interfaces: the standard Special Function Register (SFR) interface and a Configuration Interface. These SFRs allow user software the ability to enable/disable the module, program input bits into the CLB memory, select a clock source, read the outputs of each Basic Logic Element (BLE) and enable Peripheral Pin Select (PPS) outputs for specific BLE outputs.
12
12
@@ -20,15 +20,14 @@ This code example shows how to change the bitstream at run-time and will reconfi
-[PIC16F13145 Data Sheet](https://ww1.microchip.com/downloads/aemDocuments/documents/MCU08/ProductDocuments/DataSheets/PIC16F13145-Family-Microcontroller-Data-Sheet-DS40002519.pdf)
-[PIC16F13145 Content on MPLAB® Discover](https://mplab-discover.microchip.com/v2?dsl=PIC16F13145)
23
+
-[PIC16F13145 Code Examples on Discover](https://mplab-discover.microchip.com/v2?dsl=PIC16F13145)
24
24
-[PIC16F13145 Code Examples on GitHub](https://github.com/orgs/microchip-pic-avr-examples/repositories?q=pic16f13145&type=all)
25
25
26
26
## Software Used
27
27
28
-
-[MPLAB X IDE v6.15 or newer](https://www.microchip.com/en-us/tools-resources/develop/mplab-x-ide?utm_source=GitHub&utm_medium=TextLink&utm_campaign=MCU8_MMTCha_PIC16F13145&utm_content=pic16f13145-multiple-clb-configurations-mplab-mcc-github&utm_bu=MCU08)
29
-
-[MPLAB XC8 v2.46 or newer](https://www.microchip.com/en-us/tools-resources/develop/mplab-xc-compilers?utm_source=GitHub&utm_medium=TextLink&utm_campaign=MCU8_MMTCha_PIC16F13145&utm_content=pic16f13145-multiple-clb-configurations-mplab-mcc-github&utm_bu=MCU08)
-[PIC16F1xxxx_DFP Device Family Pack v1.24.387 or newer](https://packs.download.microchip.com/)
28
+
-[MPLAB® X IDE v6.20 or newer](https://www.microchip.com/en-us/tools-resources/develop/mplab-x-ide?utm_source=GitHub&utm_medium=TextLink&utm_campaign=MCU8_MMTCha_PIC16F13145&utm_content=pic16f13145-multiple-clb-configurations-mplab-mcc-github&utm_bu=MCU08)
29
+
-[MPLAB XC8 v2.50 or newer](https://www.microchip.com/en-us/tools-resources/develop/mplab-xc-compilers?utm_source=GitHub&utm_medium=TextLink&utm_campaign=MCU8_MMTCha_PIC16F13145&utm_content=pic16f13145-multiple-clb-configurations-mplab-mcc-github&utm_bu=MCU08)
30
+
-[PIC16F1xxxx_DFP Device Family Pack v1.25.389 or newer](https://packs.download.microchip.com/)
32
31
33
32
## Hardware Used
34
33
@@ -63,18 +62,18 @@ The main point of this example is showing the changes that must be made to the b
63
62
After the file has been renamed, the labels that delimit the sequence of data words and the name of the Program Section have to be changed so that they are unique for every bitstream assembly file, as demonstrated in the diagram below. Finally, the user can implement a new digital design, synthesize it and generate a new bitstream file through the MCC. The process can be reiterated however many times it is needed to create the required number of bitstream files.
64
63
65
64
<picture>
66
-
<img alt="Shows an MPLAB® Code Configurator (MCC) Configuration for the System Clock" src="images/diff.svg" width="600">
65
+
<img alt="Shows an MPLAB Code Configurator (MCC) Configuration for the System Clock" src="images/diff.svg" width="600">
67
66
</picture>
68
67
69
68
### Additional MCC Configurations
70
69
71
-
The CLB Module in the MCC also features some supplementary configurations to control the generation and loading of the bitstream file. By default, the MCC generates source code that loads the synthesized bitstream into the CLB registers and enables the module at start-up during the system initialization step. This is counter-intuitive in the context of multiple configurations because the user may want to load a specific configuration at start-up instead of the last generated one (if its default labels weren’t changed) and enable the CLB manually. This behavior may be turned off by disabling the *Load CLB Bitstream After Reset* and *Enable CLB* options in the CLB Module.
70
+
The CLB Module in the MCC also features some supplementary configurations to control the generation and loading of the bitstream file. By default, the MCC generates source code that loads the synthesized bitstream into the CLB registers and enables the module at start-up during the system initialization step. This is counter-intuitive in the context of multiple configurations because the user may want to load a specific configuration at start-up instead of the last generated one (if its default labels weren’t changed) and enable the CLB manually. This behavior may be turned off by disabling the _Load CLB Bitstream After Reset_ and _Enable CLB_ options in the CLB Module.
72
71
73
72
<picture>
74
-
<img alt="Shows an MPLAB® Code Configurator (MCC) Configuration for the CLB1 module with two options highlighted" src="images/mcc/clb1-highlight.png" width="600">
73
+
<img alt="Shows an MPLAB Code Configurator (MCC) Configuration for the CLB1 module with two options highlighted" src="images/mcc/clb1-highlight.png" width="600">
75
74
</picture>
76
75
77
-
The other important and useful configuration is the possibility of setting the starting address in Program Flash Memory where the bitstream would reside. This behavior can be turned on by enabling the *Configurable Bitstream Address* option in the CLB Module and inputing the desired value in the now available field, as long as its within the displayed constraints. Additional directives and Program Section flags are generated in order to have the bitstream values laid out in memory at the specified address. The generated preprocessor macro (`CLB_CONFIG_ADDRESS`) may also be renamed along with the other labels to maintain consistency by using the same naming scheme, but this is not mandatory since the define is local to every assembly file. Thus, the configuration for a fixed address can be enabled or disabled at will for each configuration, in case a predefined memory address is needed or not.
76
+
The other important and useful configuration is the possibility of setting the starting address in Program Flash Memory where the bitstream would reside. This behavior can be turned on by enabling the _Configurable Bitstream Address_ option in the CLB Module and inputing the desired value in the now available field, as long as its within the displayed constraints. Additional directives and Program Section flags are generated in order to have the bitstream values laid out in memory at the specified address. The generated preprocessor macro (`CLB_CONFIG_ADDRESS`) may also be renamed along with the other labels to maintain consistency by using the same naming scheme, but this is not mandatory since the define is local to every assembly file. Thus, the configuration for a fixed address can be enabled or disabled at will for each configuration, in case a predefined memory address is needed or not.
0 commit comments