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PhilippvKPhilippvK
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Merge pull request #46 from PhilippvK/llvm-19.1.0
Minor fixes
2 parents 2468f88 + e682183 commit 0924e44

23 files changed

+722
-634
lines changed

‎core_descs/Example.core_desc‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -43,5 +43,15 @@ InstructionSet XExample extends RISCVBase {
4343
}
4444
}
4545

46+
// CHECK-RV32-NEXT: Pattern for ADD3: (add (add GPR:$rs2, GPR:$rs1), GPR:$rd)
47+
// CHECK-RV64-NEXT: Pattern for ADD3: (add (add GPR:$rs2, GPR:$rs1), GPR:$rd)
48+
ADD3 {
49+
encoding: 7'b1 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000011;
50+
assembly:"{name(rd)}, {name(rs2)}({name(rs1)})";
51+
behavior: {
52+
X[rd] += X[rs1] + X[rs2];
53+
}
54+
}
55+
4656
}
4757
}

‎core_descs/Example.ll‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,3 +51,13 @@ define void @implNAND(ptr %rs2, ptr %rs1, ptr noalias %rd) {
5151
ret void
5252
}
5353

54+
define void @implADD3(ptr %rs2, ptr %rs1, ptr noalias %rd) {
55+
%rs1.v = load i64, ptr %rs1, align 8
56+
%rs2.v = load i64, ptr %rs2, align 8
57+
%1 = add i64 %rs1.v, %rs2.v
58+
%rd.v = load i64, ptr %rd, align 8
59+
%2 = add i64 %rd.v, %1
60+
store i64 %2, ptr %rd, align 8
61+
ret void
62+
}
63+

‎core_descs/Example.td‎

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,27 @@
11
let Predicates = [HasVendorXCValu] in {
22

3-
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1, Constraints = "$rd = $rd_wb" in def CV_SUBINCACC_ : RVInst_CV_SUBINCACC<(outs GPR:$rd_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rd)>;
3+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "$rd = $rd_wb" in def CV_SUBINCACC_ : RVInst_CV_SUBINCACC<(outs GPR:$rd_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rd)>;
44

55
def : Pat<
66
(i64 (add (sub (add GPR:$rs1, (i64 1)), GPR:$rs2), GPR:$rd)),
77
(CV_SUBINCACC_ GPR:$rs2, GPR:$rs1, GPR:$rd)>;
88

9-
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1, Constraints = "" in def CV_MAXU_ : RVInst_CV_MAXU<(outs GPR:$rd), (ins GPR:$rs2, GPR:$rs1)>;
9+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "" in def CV_MAXU_ : RVInst_CV_MAXU<(outs GPR:$rd), (ins GPR:$rs2, GPR:$rs1)>;
1010

1111
def : Pat<
1212
(i64 (select (i64 (setcc (i64 GPR:$rs1), (i64 GPR:$rs2), SETUGT)), GPR:$rs1, GPR:$rs2)),
1313
(CV_MAXU_ GPR:$rs2, GPR:$rs1)>;
1414

15-
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1, Constraints = "" in def NAND_ : RVInst_NAND<(outs GPR:$rd), (ins GPR:$rs2, GPR:$rs1)>;
15+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "" in def NAND_ : RVInst_NAND<(outs GPR:$rd), (ins GPR:$rs2, GPR:$rs1)>;
1616

1717
def : Pat<
1818
(i64 (xor (and GPR:$rs2, GPR:$rs1), (i64 -1))),
1919
(NAND_ GPR:$rs2, GPR:$rs1)>;
2020

21+
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "$rd = $rd_wb" in def ADD3_ : RVInst_ADD3<(outs GPR:$rd_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rd)>;
22+
23+
def : Pat<
24+
(i64 (add (add GPR:$rs2, GPR:$rs1), GPR:$rd)),
25+
(ADD3_ GPR:$rs2, GPR:$rs1, GPR:$rd)>;
26+
2127
}

‎core_descs/ExampleInstrFormat.td‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,3 +31,14 @@ class RVInst_NAND<dag outs, dag ins> : RVInst<outs, ins, "nand", "$rd, $rs1, $rs
3131
let Inst{11-7} = rd{4-0};
3232
let Inst{6-0} = 0x0;
3333
}
34+
class RVInst_ADD3<dag outs, dag ins> : RVInst<outs, ins, "add3", "$rd, $rs2($rs1)", [], InstFormatOther> {
35+
bits<5> rs2;
36+
bits<5> rs1;
37+
bits<5> rd;
38+
let Inst{31-25} = 0x0;
39+
let Inst{24-20} = rs2{4-0};
40+
let Inst{19-15} = rs1{4-0};
41+
let Inst{14-12} = 0x0;
42+
let Inst{11-7} = rd{4-0};
43+
let Inst{6-0} = 0x0;
44+
}

‎core_descs/ExampleMemory.core_desc‎

Lines changed: 5 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,8 @@
1+
// RUN: pattern-gen %s -O 3 --mattr=+m --riscv-xlen 64 | FileCheck --check-prefixes=CHECK-RV64,CHECK-RV64-EXTEND -allow-unused-prefixes %s
2+
// RUN: pattern-gen %s -O 3 --no-extend --mattr=+m --riscv-xlen 64 | FileCheck --check-prefixes=CHECK-RV64,CHECK-RV64-NOEXTED -allow-unused-prefixes %s
13

24

5+
// CHECK-RV64: Pattern for LDR: (i64 (load (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 (shl (i64 GPR:$rs2), (i64 (i64 uimm5:$imm)))))))))
36
LDR {
47
encoding: 2'b0 :: imm[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000011;
58
assembly:"{name(rd)}, {imm} {name(rs2)}({name(rs1)})";
@@ -10,6 +13,7 @@ LDR {
1013
}
1114
}
1215

16+
// CHECK-RV64: Pattern for STR: (store (XLenVT GPR:$rs3), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 (shl (i64 GPR:$rs2), (i64 (i64 uimm5:$imm))))))))
1317
STR {
1418
encoding: 2'b1 :: rs3[4:0] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: imm[4:0] :: 7'b0000011;
1519
assembly:"{name(rs3)}, {imm} {name(rs2)}({name(rs1)})";
@@ -19,14 +23,7 @@ STR {
1923
}
2024
}
2125

22-
ADD3 {
23-
encoding: 7'b1 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000011;
24-
assembly:"{name(rd)}, {name(rs2)}({name(rs1)})";
25-
behavior: {
26-
X[rd] += X[rs1] + X[rs2];
27-
}
28-
}
29-
26+
// CHECK-RV64: Pattern for LOADMAC: (add GPR:$rd, (mul (i64 (load GPR:$rs2)), (i64 (load GPR:$rs1))))
3027
LOADMAC {
3128
encoding: 7'd40 :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000011;
3229
assembly:"{name(rd)}, ({name(rs2)}), ({name(rs1)})";

‎core_descs/ExampleMemory.ll‎

Lines changed: 22 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -8,25 +8,22 @@ define void @implLDR(i64 %imm, ptr %rs2, ptr %rs1, ptr noalias %rd) {
88
%rs2.v = load i64, ptr %rs2, align 8
99
%3 = shl i64 %rs2.v, %imm
1010
%rs1.v = load i64, ptr %rs1, align 8
11-
%4 = zext i64 %rs1.v to i128
12-
%5 = zext i64 %3 to i128
13-
%6 = add i128 %4, %5
14-
%7 = trunc i128 %6 to i64
15-
%8 = alloca i64, align 8
16-
store i64 %7, ptr %8, align 4
17-
%.v = load i64, ptr %8, align 8
18-
%9 = inttoptr i64 %.v to ptr
19-
%.v1 = load i64, ptr %9, align 8
20-
%10 = alloca i64, align 8
21-
store i64 %.v1, ptr %10, align 4
22-
br i1 true, label %11, label %12
11+
%4 = add i64 %rs1.v, %3
12+
%5 = alloca i64, align 8
13+
store i64 %4, ptr %5, align 4
14+
%.v = load i64, ptr %5, align 8
15+
%6 = inttoptr i64 %.v to ptr
16+
%.v1 = load i64, ptr %6, align 8
17+
%7 = alloca i64, align 8
18+
store i64 %.v1, ptr %7, align 4
19+
br i1 true, label %8, label %9
2320

24-
11: ; preds = %0
25-
%.v2 = load i64, ptr %10, align 8
21+
8: ; preds = %0
22+
%.v2 = load i64, ptr %7, align 8
2623
store i64 %.v2, ptr %rd, align 8
27-
br label %12
24+
br label %9
2825

29-
12: ; preds = %11, %0
26+
9: ; preds = %8, %0
3027
ret void
3128
}
3229

@@ -40,31 +37,13 @@ define void @implSTR(ptr %rs3, ptr %rs2, ptr %rs1, i64 %imm) {
4037
%rs2.v = load i64, ptr %rs2, align 8
4138
%3 = shl i64 %rs2.v, %imm
4239
%rs1.v = load i64, ptr %rs1, align 8
43-
%4 = zext i64 %rs1.v to i128
44-
%5 = zext i64 %3 to i128
45-
%6 = add i128 %4, %5
46-
%7 = trunc i128 %6 to i64
47-
%8 = alloca i64, align 8
48-
store i64 %7, ptr %8, align 4
49-
%.v = load i64, ptr %8, align 8
50-
%9 = inttoptr i64 %.v to ptr
40+
%4 = add i64 %rs1.v, %3
41+
%5 = alloca i64, align 8
42+
store i64 %4, ptr %5, align 4
43+
%.v = load i64, ptr %5, align 8
44+
%6 = inttoptr i64 %.v to ptr
5145
%rs3.v = load i64, ptr %rs3, align 8
52-
store i64 %rs3.v, ptr %9, align 8
53-
ret void
54-
}
55-
56-
define void @implADD3(ptr %rs2, ptr %rs1, ptr noalias %rd) {
57-
%rs1.v = load i64, ptr %rs1, align 8
58-
%rs2.v = load i64, ptr %rs2, align 8
59-
%1 = zext i64 %rs1.v to i128
60-
%2 = zext i64 %rs2.v to i128
61-
%3 = add i128 %1, %2
62-
%rd.v = load i64, ptr %rd, align 8
63-
%4 = zext i64 %rd.v to i256
64-
%5 = zext i128 %3 to i256
65-
%6 = add i256 %4, %5
66-
%7 = trunc i256 %6 to i64
67-
store i64 %7, ptr %rd, align 8
46+
store i64 %rs3.v, ptr %6, align 8
6847
ret void
6948
}
7049

@@ -75,15 +54,10 @@ define void @implLOADMAC(ptr %rs2, ptr %rs1, ptr noalias %rd) {
7554
%2 = inttoptr i64 %rs2.v to ptr
7655
%.v = load i64, ptr %1, align 8
7756
%.v1 = load i64, ptr %2, align 8
78-
%3 = zext i64 %.v to i128
79-
%4 = zext i64 %.v1 to i128
80-
%5 = mul i128 %3, %4
57+
%3 = mul i64 %.v, %.v1
8158
%rd.v = load i64, ptr %rd, align 8
82-
%6 = zext i64 %rd.v to i256
83-
%7 = zext i128 %5 to i256
84-
%8 = add i256 %6, %7
85-
%9 = trunc i256 %8 to i64
86-
store i64 %9, ptr %rd, align 8
59+
%4 = add i64 %rd.v, %3
60+
store i64 %4, ptr %rd, align 8
8761
ret void
8862
}
8963

‎core_descs/ExampleMemory.td‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -12,12 +12,6 @@ def : Pat<
1212
(store (XLenVT GPR:$rs3), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i64 (i64 (shl (i64 GPR:$rs2), (i64 (i64 uimm5:$imm)))))))),
1313
(STR_ GPR:$rs3, GPR:$rs2, GPR:$rs1, uimm5:$imm)>;
1414

15-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "$rd = $rd_wb" in def ADD3_ : RVInst_ADD3<(outs GPR:$rd_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rd)>;
16-
17-
def : Pat<
18-
(i64 (add (add GPR:$rs2, GPR:$rs1), GPR:$rd)),
19-
(ADD3_ GPR:$rs2, GPR:$rs1, GPR:$rd)>;
20-
2115
let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isCodeGenOnly = 1, Constraints = "$rd = $rd_wb" in def LOADMAC_ : RVInst_LOADMAC<(outs GPR:$rd_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rd)>;
2216

2317
def : Pat<

‎core_descs/ExampleMemoryInstrFormat.core_desc‎

Whitespace-only changes.

‎core_descs/ExampleMemoryInstrFormat.td‎

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -24,17 +24,6 @@ class RVInst_STR<dag outs, dag ins> : RVInst<outs, ins, "str", "$rs3, $imm $rs2(
2424
let Inst{11-7} = imm{4-0};
2525
let Inst{6-0} = 0x0;
2626
}
27-
class RVInst_ADD3<dag outs, dag ins> : RVInst<outs, ins, "add3", "$rd, $rs2($rs1)", [], InstFormatOther> {
28-
bits<5> rs2;
29-
bits<5> rs1;
30-
bits<5> rd;
31-
let Inst{31-25} = 0x0;
32-
let Inst{24-20} = rs2{4-0};
33-
let Inst{19-15} = rs1{4-0};
34-
let Inst{14-12} = 0x0;
35-
let Inst{11-7} = rd{4-0};
36-
let Inst{6-0} = 0x0;
37-
}
3827
class RVInst_LOADMAC<dag outs, dag ins> : RVInst<outs, ins, "loadmac", "$rd, ($rs2), ($rs1)", [], InstFormatOther> {
3928
bits<5> rs2;
4029
bits<5> rs1;

‎core_descs/ExampleRV32.core_desc‎

Lines changed: 48 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,13 @@ InstructionSet XExampleRV32 extends RISCVBase {
55

66
instructions {
77

8-
// CHECK-RV32: Pattern for LB: (i32 (sextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 uimm12:$imm))))))
8+
// CHECK-RV32: Pattern for LB: (i32 (sextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
99
LB {
10+
operands: {
11+
unsigned<5> rd;
12+
unsigned<5> rs1;
13+
signed<12> imm;
14+
}
1015
encoding: imm[11:0] :: rs1[4:0] :: 3'b000 :: rd[4:0] :: 7'b0000011;
1116
assembly:"{name(rd)}, {imm}({name(rs1)})";
1217
behavior: {
@@ -16,8 +21,13 @@ InstructionSet XExampleRV32 extends RISCVBase {
1621
}
1722
}
1823

19-
// CHECK-RV32-NEXT: Pattern for LH: (i32 (sextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 uimm12:$imm))))))
24+
// CHECK-RV32-NEXT: Pattern for LH: (i32 (sextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
2025
LH {
26+
operands: {
27+
unsigned<5> rd;
28+
unsigned<5> rs1;
29+
signed<12> imm;
30+
}
2131
encoding: imm[11:0] :: rs1[4:0] :: 3'b001 :: rd[4:0] :: 7'b0000011;
2232
assembly:"{name(rd)}, {imm}({name(rs1)})";
2333
behavior: {
@@ -27,8 +37,13 @@ InstructionSet XExampleRV32 extends RISCVBase {
2737
}
2838
}
2939

30-
// CHECK-RV32-NEXT: Pattern for LW: (i32 (load (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 uimm12:$imm))))))
40+
// CHECK-RV32-NEXT: Pattern for LW: (i32 (load (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
3141
LW {
42+
operands: {
43+
unsigned<5> rd;
44+
unsigned<5> rs1;
45+
signed<12> imm;
46+
}
3247
encoding: imm[11:0] :: rs1[4:0] :: 3'b010 :: rd[4:0] :: 7'b0000011;
3348
assembly:"{name(rd)}, {imm}({name(rs1)})";
3449
behavior: {
@@ -38,8 +53,13 @@ InstructionSet XExampleRV32 extends RISCVBase {
3853
}
3954
}
4055

41-
// CHECK-RV32-NEXT: Pattern for LBU: (i32 (zextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 uimm12:$imm))))))
56+
// CHECK-RV32-NEXT: Pattern for LBU: (i32 (zextloadi8 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
4257
LBU {
58+
operands: {
59+
unsigned<5> rd;
60+
unsigned<5> rs1;
61+
signed<12> imm;
62+
}
4363
encoding: imm[11:0] :: rs1[4:0] :: 3'b100 :: rd[4:0] :: 7'b0000011;
4464
assembly:"{name(rd)}, {imm}({name(rs1)})";
4565
behavior: {
@@ -49,8 +69,13 @@ InstructionSet XExampleRV32 extends RISCVBase {
4969
}
5070
}
5171

52-
// CHECK-RV32-NEXT: Pattern for LHU: (i32 (zextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 uimm12:$imm))))))
72+
// CHECK-RV32-NEXT: Pattern for LHU: (i32 (zextloadi16 (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm))))))
5373
LHU {
74+
operands: {
75+
unsigned<5> rd;
76+
unsigned<5> rs1;
77+
signed<12> imm;
78+
}
5479
encoding: imm[11:0] :: rs1[4:0] :: 3'b101 :: rd[4:0] :: 7'b0000011;
5580
assembly:"{name(rd)}, {imm}({name(rs1)})";
5681
behavior: {
@@ -60,8 +85,13 @@ InstructionSet XExampleRV32 extends RISCVBase {
6085
}
6186
}
6287

63-
// CHECK-RV32-NEXT: Pattern for SB: (truncstorei8 (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 uimm12:$imm)))))
88+
// CHECK-RV32-NEXT: Pattern for SB: (truncstorei8 (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm)))))
6489
SB {
90+
operands: {
91+
unsigned<5> rs1;
92+
unsigned<5> rs2;
93+
signed<12> imm;
94+
}
6595
encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b000 :: imm[4:0] :: 7'b0100011;
6696
assembly:"{name(rs2)}, {imm}({name(rs1)})";
6797
behavior: {
@@ -70,8 +100,13 @@ InstructionSet XExampleRV32 extends RISCVBase {
70100
}
71101
}
72102

73-
// CHECK-RV32-NEXT: Pattern for SH: (truncstorei16 (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 uimm12:$imm)))))
103+
// CHECK-RV32-NEXT: Pattern for SH: (truncstorei16 (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm)))))
74104
SH {
105+
operands: {
106+
unsigned<5> rs1;
107+
unsigned<5> rs2;
108+
signed<12> imm;
109+
}
75110
encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b001 :: imm[4:0] :: 7'b0100011;
76111
assembly:"{name(rs2)}, {imm}({name(rs1)})";
77112
behavior: {
@@ -80,8 +115,13 @@ InstructionSet XExampleRV32 extends RISCVBase {
80115
}
81116
}
82117

83-
// CHECK-RV32-NEXT: Pattern for SW: (store (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 uimm12:$imm)))))
118+
// CHECK-RV32-NEXT: Pattern for SW: (store (XLenVT GPR:$rs2), (iPTR (ptradd (iPTR (iPTR GPR:$rs1)), (i32 (i32 simm12:$imm)))))
84119
SW {
120+
operands: {
121+
unsigned<5> rs1;
122+
unsigned<5> rs2;
123+
signed<12> imm;
124+
}
85125
encoding: imm[11:5] :: rs2[4:0] :: rs1[4:0] :: 3'b010 :: imm[4:0] :: 7'b0100011;
86126
assembly:"{name(rs2)}, {imm}({name(rs1)})";
87127
behavior: {

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