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elliotb-lowriscelliotb-lowrisc
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Add glitch filters to I^2C inputs
I^2C Fast-mode requires a 50 ns glitch filter on SCL and SDA inputs. This is an attempt at implementing such a filter using the existing prim_filter IP. Note, as it is operating in the digital domain it could fall victim to inexact clock division. Happily the clock divides nicely at our current 40 MHz system clock.
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-37
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3 files changed

+158
-37
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‎rtl/system/sonata_system.sv‎

Lines changed: 39 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -868,11 +868,47 @@ module sonata_system
868868
logic i2c_scl_h2d [I2C_NUM];
869869
logic i2c_scl_en_h2d[I2C_NUM];
870870
logic i2c_scl_d2h [I2C_NUM];
871+
logic i2c_scl_d2h_f [I2C_NUM];
871872
logic i2c_sda_h2d [I2C_NUM];
872873
logic i2c_sda_en_h2d[I2C_NUM];
873874
logic i2c_sda_d2h [I2C_NUM];
875+
logic i2c_sda_d2h_f [I2C_NUM];
876+
// Calculate the number whole clock cycles that fit in a 50 ns period.
877+
// Round downwards (rather then to the nearest) to avoid violating the 50 ns
878+
// maximum pulse width specification for the filter.
879+
localparam int unsigned I2CFilterCycles = int'($floor(50e-9 * SysClkFreq));
874880
for (genvar i = 0; i < I2C_NUM; i++) begin : gen_i2c_hosts
875-
i2c u_i2c (
881+
// SCL & SDA input glitch filters for I^2C Fast-mode.
882+
// Enable asynchronous input synchronisers in filters to avoid
883+
// metastability issues.
884+
prim_filter #(
885+
.AsyncOn ( 1 ),
886+
.Cycles ( I2CFilterCycles )
887+
) u_i2c_filter_scl (
888+
.clk_i (clk_sys_i),
889+
.rst_ni (rst_sys_ni),
890+
.enable_i (1'b1),
891+
.filter_i (i2c_scl_d2h[i]),
892+
.filter_o (i2c_scl_d2h_f[i])
893+
);
894+
prim_filter #(
895+
.AsyncOn ( 1 ),
896+
.Cycles ( I2CFilterCycles )
897+
) u_i2c_filter_sda (
898+
.clk_i (clk_sys_i),
899+
.rst_ni (rst_sys_ni),
900+
.enable_i (1'b1),
901+
.filter_i (i2c_sda_d2h[i]),
902+
.filter_o (i2c_sda_d2h_f[i])
903+
);
904+
905+
// I^2C host.
906+
// Async input synchronisation done in filters, so removed from i2c_core
907+
// with a vendoring patch file.
908+
// Need to account for extra delay introduced by filter and external sync.
909+
i2c #(
910+
.InputDelayCycles ( 2 + I2CFilterCycles )
911+
) u_i2c (
876912
.clk_i (clk_sys_i),
877913
.rst_ni (rst_sys_ni),
878914
.ram_cfg_i (10'b0),
@@ -882,10 +918,10 @@ module sonata_system
882918
.tl_o (tl_i2c_d2h[i]),
883919

884920
// Generic IO.
885-
.cio_scl_i (i2c_scl_d2h [i]),
921+
.cio_scl_i (i2c_scl_d2h_f [i]),
886922
.cio_scl_o (i2c_scl_h2d [i]),
887923
.cio_scl_en_o (i2c_scl_en_h2d[i]),
888-
.cio_sda_i (i2c_sda_d2h [i]),
924+
.cio_sda_i (i2c_sda_d2h_f [i]),
889925
.cio_sda_o (i2c_sda_h2d [i]),
890926
.cio_sda_en_o (i2c_sda_en_h2d[i]),
891927

‎vendor/lowrisc_ip/ip/i2c/rtl/i2c_core.sv‎

Lines changed: 11 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -48,10 +48,10 @@ module i2c_core import i2c_pkg::*;
4848
localparam int unsigned MaxFifoDepthW = 12;
4949

5050
// Round-trip delay for outputs to appear on the inputs, not including rise
51-
// time. This is the input delay external to this IP, plus the output flop,
52-
// plus the 2-flop synchronizer on the input. The total value here
51+
// time. This is the input delay external to this IP, plus the output flop.
52+
// The total value here
5353
// represents the minimum allowed high and low times for SCL.
54-
localparam int unsigned RoundTripCycles = InputDelayCycles + 2 + 1;
54+
localparam int unsigned RoundTripCycles = InputDelayCycles + 1;
5555

5656
logic [12:0] thigh;
5757
logic [12:0] tlow;
@@ -72,8 +72,6 @@ module i2c_core import i2c_pkg::*;
7272
logic [30:0] host_nack_handler_timeout;
7373
logic host_nack_handler_timeout_en;
7474

75-
logic scl_sync;
76-
logic sda_sync;
7775
logic scl_out_controller_fsm, sda_out_controller_fsm;
7876
logic scl_out_target_fsm, sda_out_target_fsm;
7977
logic scl_out_fsm;
@@ -428,27 +426,6 @@ module i2c_core import i2c_pkg::*;
428426
assign acq_fifo_rready = (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) |
429427
(target_loopback & (tx_fifo_wready | (acq_type != AcqData)));
430428

431-
// sync the incoming SCL and SDA signals
432-
prim_flop_2sync #(
433-
.Width(1),
434-
.ResetValue(1'b1)
435-
) u_i2c_sync_scl (
436-
.clk_i,
437-
.rst_ni,
438-
.d_i (scl_i),
439-
.q_o (scl_sync)
440-
);
441-
442-
prim_flop_2sync #(
443-
.Width(1),
444-
.ResetValue(1'b1)
445-
) u_i2c_sync_sda (
446-
.clk_i,
447-
.rst_ni,
448-
.d_i (sda_i),
449-
.q_o (sda_sync)
450-
);
451-
452429
// Various bus collision events are detected while SCL is high.
453430
logic sda_fsm, sda_fsm_q;
454431
logic scl_fsm, scl_fsm_q;
@@ -483,7 +460,7 @@ module i2c_core import i2c_pkg::*;
483460
end
484461
end
485462
assign bus_event_detect = (bus_event_detect_cnt == '0);
486-
assign sda_released_but_low = bus_event_detect && scl_sync && (sda_fsm_q != sda_sync);
463+
assign sda_released_but_low = bus_event_detect && scl_i && (sda_fsm_q != sda_i);
487464
// What about unexpected start / stop on the bits that are read?
488465
assign controller_sda_interference = controller_transmitting && sda_released_but_low;
489466
assign target_arbitration_lost = target_transmitting && sda_released_but_low;
@@ -496,8 +473,8 @@ module i2c_core import i2c_pkg::*;
496473
.clk_i,
497474
.rst_ni,
498475

499-
.scl_i (scl_sync),
500-
.sda_i (sda_sync),
476+
.scl_i (scl_i),
477+
.sda_i (sda_i),
501478

502479
.controller_enable_i (host_enable),
503480
.multi_controller_enable_i (reg2hw.ctrl.multi_controller_monitor_en.q),
@@ -523,9 +500,9 @@ module i2c_core import i2c_pkg::*;
523500
.clk_i,
524501
.rst_ni,
525502

526-
.scl_i (scl_sync),
503+
.scl_i (scl_i),
527504
.scl_o (scl_out_controller_fsm),
528-
.sda_i (sda_sync),
505+
.sda_i (sda_i),
529506
.sda_o (sda_out_controller_fsm),
530507
.bus_free_i (bus_free),
531508
.transmitting_o (controller_transmitting),
@@ -579,9 +556,9 @@ module i2c_core import i2c_pkg::*;
579556
.clk_i,
580557
.rst_ni,
581558

582-
.scl_i (scl_sync),
559+
.scl_i (scl_i),
583560
.scl_o (scl_out_target_fsm),
584-
.sda_i (sda_sync),
561+
.sda_i (sda_i),
585562
.sda_o (sda_out_target_fsm),
586563
.start_detect_i (start_detect),
587564
.stop_detect_i (stop_detect),
@@ -881,7 +858,7 @@ module i2c_core import i2c_pkg::*;
881858
// TODO: Decide whether to keep this assertion. It is primarily checking the
882859
// testbench, not the IP, due to the CDC cycle deletion.
883860
// Check to make sure scl_i is never a single cycle glitch
884-
// `ASSERT(SclInputGlitch_A, $rose(scl_sync) |-> ##1 scl_sync)
861+
// `ASSERT(SclInputGlitch_A, $rose(scl_i) |-> ##1 scl_i)
885862

886863
`ASSERT_INIT(FifoDepthValid_A, FifoDepth > 0 && FifoDepthW <= MaxFifoDepthW)
887864
`ASSERT_INIT(AcqFifoDepthValid_A, AcqFifoDepth > 0 && AcqFifoDepthW <= MaxFifoDepthW)

‎vendor/patches/lowrisc_ip/i2c/0004-Remove-Synchronisers.patch‎

Lines changed: 108 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,108 @@
1+
diff --git a/rtl/i2c_core.sv b/rtl/i2c_core.sv
2+
index af8c0ae..927fda8 100644
3+
--- a/rtl/i2c_core.sv
4+
+++ b/rtl/i2c_core.sv
5+
@@ -48,10 +48,10 @@ module i2c_core import i2c_pkg::*;
6+
localparam int unsigned MaxFifoDepthW = 12;
7+
8+
// Round-trip delay for outputs to appear on the inputs, not including rise
9+
- // time. This is the input delay external to this IP, plus the output flop,
10+
- // plus the 2-flop synchronizer on the input. The total value here
11+
+ // time. This is the input delay external to this IP, plus the output flop.
12+
+ // The total value here
13+
// represents the minimum allowed high and low times for SCL.
14+
- localparam int unsigned RoundTripCycles = InputDelayCycles + 2 + 1;
15+
+ localparam int unsigned RoundTripCycles = InputDelayCycles + 1;
16+
17+
logic [12:0] thigh;
18+
logic [12:0] tlow;
19+
@@ -72,8 +72,6 @@ module i2c_core import i2c_pkg::*;
20+
logic [30:0] host_nack_handler_timeout;
21+
logic host_nack_handler_timeout_en;
22+
23+
- logic scl_sync;
24+
- logic sda_sync;
25+
logic scl_out_controller_fsm, sda_out_controller_fsm;
26+
logic scl_out_target_fsm, sda_out_target_fsm;
27+
logic scl_out_fsm;
28+
@@ -428,27 +426,6 @@ module i2c_core import i2c_pkg::*;
29+
assign acq_fifo_rready = (reg2hw.acqdata.abyte.re & reg2hw.acqdata.signal.re) |
30+
(target_loopback & (tx_fifo_wready | (acq_type != AcqData)));
31+
32+
- // sync the incoming SCL and SDA signals
33+
- prim_flop_2sync #(
34+
- .Width(1),
35+
- .ResetValue(1'b1)
36+
- ) u_i2c_sync_scl (
37+
- .clk_i,
38+
- .rst_ni,
39+
- .d_i (scl_i),
40+
- .q_o (scl_sync)
41+
- );
42+
-
43+
- prim_flop_2sync #(
44+
- .Width(1),
45+
- .ResetValue(1'b1)
46+
- ) u_i2c_sync_sda (
47+
- .clk_i,
48+
- .rst_ni,
49+
- .d_i (sda_i),
50+
- .q_o (sda_sync)
51+
- );
52+
-
53+
// Various bus collision events are detected while SCL is high.
54+
logic sda_fsm, sda_fsm_q;
55+
logic scl_fsm, scl_fsm_q;
56+
@@ -483,7 +460,7 @@ module i2c_core import i2c_pkg::*;
57+
end
58+
end
59+
assign bus_event_detect = (bus_event_detect_cnt == '0);
60+
- assign sda_released_but_low = bus_event_detect && scl_sync && (sda_fsm_q != sda_sync);
61+
+ assign sda_released_but_low = bus_event_detect && scl_i && (sda_fsm_q != sda_i);
62+
// What about unexpected start / stop on the bits that are read?
63+
assign controller_sda_interference = controller_transmitting && sda_released_but_low;
64+
assign target_arbitration_lost = target_transmitting && sda_released_but_low;
65+
@@ -496,8 +473,8 @@ module i2c_core import i2c_pkg::*;
66+
.clk_i,
67+
.rst_ni,
68+
69+
- .scl_i (scl_sync),
70+
- .sda_i (sda_sync),
71+
+ .scl_i (scl_i),
72+
+ .sda_i (sda_i),
73+
74+
.controller_enable_i (host_enable),
75+
.multi_controller_enable_i (reg2hw.ctrl.multi_controller_monitor_en.q),
76+
@@ -523,9 +500,9 @@ module i2c_core import i2c_pkg::*;
77+
.clk_i,
78+
.rst_ni,
79+
80+
- .scl_i (scl_sync),
81+
+ .scl_i (scl_i),
82+
.scl_o (scl_out_controller_fsm),
83+
- .sda_i (sda_sync),
84+
+ .sda_i (sda_i),
85+
.sda_o (sda_out_controller_fsm),
86+
.bus_free_i (bus_free),
87+
.transmitting_o (controller_transmitting),
88+
@@ -579,9 +556,9 @@ module i2c_core import i2c_pkg::*;
89+
.clk_i,
90+
.rst_ni,
91+
92+
- .scl_i (scl_sync),
93+
+ .scl_i (scl_i),
94+
.scl_o (scl_out_target_fsm),
95+
- .sda_i (sda_sync),
96+
+ .sda_i (sda_i),
97+
.sda_o (sda_out_target_fsm),
98+
.start_detect_i (start_detect),
99+
.stop_detect_i (stop_detect),
100+
@@ -881,7 +858,7 @@ module i2c_core import i2c_pkg::*;
101+
// TODO: Decide whether to keep this assertion. It is primarily checking the
102+
// testbench, not the IP, due to the CDC cycle deletion.
103+
// Check to make sure scl_i is never a single cycle glitch
104+
- // `ASSERT(SclInputGlitch_A, $rose(scl_sync) |-> ##1 scl_sync)
105+
+ // `ASSERT(SclInputGlitch_A, $rose(scl_i) |-> ##1 scl_i)
106+
107+
`ASSERT_INIT(FifoDepthValid_A, FifoDepth > 0 && FifoDepthW <= MaxFifoDepthW)
108+
`ASSERT_INIT(AcqFifoDepthValid_A, AcqFifoDepth > 0 && AcqFifoDepthW <= MaxFifoDepthW)

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