fix vc4-stage1

Author: cleverca22

app/vc4-stage1/stage1.c

@@ -11,7 +11,7 @@
 #include <lk/reg.h>
 #include <platform.h>
 #include <platform/bcm28xx/pll_read.h>
-#include <platform/bcm28xx/pm.h>
+#include <platform/bcm28xx/power.h>
 #include <platform/bcm28xx/sdhost_impl.h>
 #include <platform/bcm28xx/sdram.h>
 #include <string.h>

platform/bcm28xx/rpi-ddr2/sdram.c

@@ -24,7 +24,7 @@ VideoCoreIV SDRAM initialization code.
 #include <lk/reg.h>
 #include <platform/bcm28xx.h>
 #include <platform/bcm28xx/pll.h>
-#include <platform/bcm28xx/pm.h>
+#include <platform/bcm28xx/power.h>
 #include <platform/bcm28xx/sdram.h>
 #include <platform/bcm28xx/udelay.h>
 #include <stdbool.h>

platform/bcm28xx/rules.mk

@@ -5,6 +5,7 @@ MODULE := $(LOCAL_DIR)
 WITH_SMP := 1
 #SMP_MAX_CPUS ?= 1
 #LK_HEAP_IMPLEMENTATION ?= dlmalloc
+MODULE_DEPS += platform/bcm28xx/power
 
 ifeq ($(ARCH),vpu)
   MODULE_DEPS += platform/bcm28xx/pll
@@ -19,7 +20,6 @@ ifeq ($(ARCH),vpu)
   endif
   GLOBAL_DEFINES += SMP_MAX_CPUS=1
 else # it must be arm32 or arm64
-  MODULE_DEPS += platform/bcm28xx/power
   ifeq ($(HAVE_ARM_TIMER),1)
     MODULE_DEPS += dev/timer/arm_generic
     GLOBAL_DEFINES += HAVE_ARM_TIMER=1