From 58e7f647ab97d5dee45b2a9fe028317ac2cac3be Mon Sep 17 00:00:00 2001
From: Darren Kulp <darren@kulp.ch>
Date: Wed, 5 Aug 2020 09:04:25 -0700
Subject: [PATCH] Demonstrate building a top-level with Verilator

---
 hw/verilator/.gitignore   | 11 +++++++
 hw/verilator/Makefile     | 33 +++++++++++++++++++
 hw/verilator/sim_main.cpp | 67 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 111 insertions(+)
 create mode 100644 hw/verilator/.gitignore
 create mode 100644 hw/verilator/Makefile
 create mode 100644 hw/verilator/sim_main.cpp

diff --git a/hw/verilator/.gitignore b/hw/verilator/.gitignore
new file mode 100644
index 000000000..e0a7f952d
--- /dev/null
+++ b/hw/verilator/.gitignore
@@ -0,0 +1,11 @@
+*.tree
+*.dot
+Vtop*.cpp
+Vtop*.h
+Vtop*.mk
+Vtop*.vpp
+Vtop
+Vtop.xml
+Vtop*.a
+Vtop__*.*
+Vtop_061_order_edges.txt
diff --git a/hw/verilator/Makefile b/hw/verilator/Makefile
new file mode 100644
index 000000000..e5e4e0076
--- /dev/null
+++ b/hw/verilator/Makefile
@@ -0,0 +1,33 @@
+include Vtop.mk
+
+vpath %.v $(CURDIR)/../verilog
+vpath %.v $(CURDIR)/../../3rdparty/wb_intercon/rtl/verilog
+
+VFILES += top.v
+VFILES += sim/simclocks.v
+VFILES += tenyr.v
+VFILES += ram.v
+VFILES += seg7.v
+VFILES += hex2segments.v
+VFILES += gpio.v
+VFILES += wb_mux.v
+
+VFLAGS += -Wall
+VFLAGS += -Wno-fatal
+VFLAGS += -Wno-style
+
+VFLAGS += -I$(CURDIR)/../verilog
+VFLAGS += --cc --trace
+VFLAGS += -DSIMCLK=tenyr_mainclock
+VFLAGS += --Mdir $(CURDIR)
+VFLAGS += --exe
+# TODO drop --public-flat-rw
+VFLAGS += --vpi --public-flat-rw
+
+ifeq ($(DEBUG),1)
+VFLAGS += --debug
+CPPFLAGS += -DVL_DEBUG
+endif
+
+Vtop.mk: $(VFILES) sim_main.cpp
+	verilator $(VFLAGS) $^
diff --git a/hw/verilator/sim_main.cpp b/hw/verilator/sim_main.cpp
new file mode 100644
index 000000000..6dec13ca2
--- /dev/null
+++ b/hw/verilator/sim_main.cpp
@@ -0,0 +1,67 @@
+#include "Vtop.h"
+
+// If "verilator --trace" is used, include the tracing class
+#if VM_TRACE
+# include <verilated_vcd_c.h>
+#endif
+
+static const vluint64_t MAX_TIME = 1000000u;
+
+// Current simulation time (64-bit unsigned)
+vluint64_t main_time = 0;
+// Called by $time in Verilog
+double sc_time_stamp()
+{
+    return static_cast< double >( main_time );  // Note does conversion to real, to match SystemC
+}
+
+static inline bool finished(const Vtop &top)
+{
+    return main_time >= MAX_TIME
+        || Verilated::gotFinish()
+        || (top.reset == 0 && top.Tenyr__DOT__core__DOT__nextP == 0);
+}
+
+int main(int argc, char* argv[])
+{
+    Verilated::commandArgs(argc, argv);
+
+    Vtop top;
+
+#if VM_TRACE
+    // If verilator was invoked with --trace argument,
+    // and if at run time passed the +trace argument, turn on tracing
+    VerilatedVcdC* tfp = NULL;
+    const char* flag = Verilated::commandArgsPlusMatch("trace");
+    if (flag && 0==strcmp(flag, "+trace")) {
+        Verilated::traceEverOn(true);  // Verilator must compute traced signals
+        VL_PRINTF("Enabling waves into logs/vlt_dump.vcd...\n");
+        tfp = new VerilatedVcdC;
+        top.trace(tfp, 99);  // Trace 99 levels of hierarchy
+        Verilated::mkdir("logs");
+        tfp->open("logs/vlt_dump.vcd");  // Open the dump file
+    }
+#endif
+
+    top.reset = 1;
+    top.clk = 0;
+
+    while (!finished(top)) {
+        top.clk = !top.clk;
+        if (main_time < 10)
+            top.Tenyr__DOT__core__DOT__nextP = 0x1000;
+        if (main_time > 10)
+            top.reset = 0;
+        top.eval();
+        printf("P = %08x\n", top.Tenyr__DOT__core__DOT__nextP);
+
+#if VM_TRACE
+        // Dump trace data for this cycle
+        if (tfp) tfp->dump(main_time);
+#endif
+
+        main_time++;
+    }
+
+    top.final();
+}