Proc codegen with `--generator=combinational` can drop incoming data

[ericastor]

Describe the bug
When running combinational codegen on a proc, the resulting Verilog can signal ready prematurely on some channels, resulting in potential data loss.

To Reproduce
Steps to reproduce the behavior:

1. Codegen a proc with receives on two channels (A and B) and a send on a third channel C.
2. Signal valid on channel A and ready on channel C; do not signal valid on channel B.
3. Observe that the proc signals ready on channel A, despite not signaling valid on channel C.

Assuming ready/valid handshakes are respected, this will consume the data from channel A & effectively drop it.

Expected behavior
A proc should not signal ready on a receiving channel unless it will definitely handle the data if the channel signaled valid at the same time.