cmd/compile: support Zba extensions in riscv64 compiler

Add compiler support for Zba entensions, which are mandatory in the
rva22u64 profile. These can be used to accelerate address computation.

Author: yaduo.wang

src/cmd/compile/internal/riscv64/ssa.go

@@ -294,7 +294,8 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
 		ssa.OpRISCV64FADDD, ssa.OpRISCV64FSUBD, ssa.OpRISCV64FMULD, ssa.OpRISCV64FDIVD,
 		ssa.OpRISCV64FEQD, ssa.OpRISCV64FNED, ssa.OpRISCV64FLTD, ssa.OpRISCV64FLED, ssa.OpRISCV64FSGNJD,
 		ssa.OpRISCV64MIN, ssa.OpRISCV64MAX, ssa.OpRISCV64MINU, ssa.OpRISCV64MAXU,
-		ssa.OpRISCV64SH1ADD, ssa.OpRISCV64SH2ADD, ssa.OpRISCV64SH3ADD:
+		ssa.OpRISCV64SH1ADD, ssa.OpRISCV64SH2ADD, ssa.OpRISCV64SH3ADD,
+		ssa.OpRISCV64ADDUW, ssa.OpRISCV64SH1ADDUW, ssa.OpRISCV64SH2ADDUW, ssa.OpRISCV64SH3ADDUW:
 		r := v.Reg()
 		r1 := v.Args[0].Reg()
 		r2 := v.Args[1].Reg()
@@ -433,7 +434,7 @@ func ssaGenValue(s *ssagen.State, v *ssa.Value) {
 	case ssa.OpRISCV64ADDI, ssa.OpRISCV64ADDIW, ssa.OpRISCV64XORI, ssa.OpRISCV64ORI, ssa.OpRISCV64ANDI,
 		ssa.OpRISCV64SLLI, ssa.OpRISCV64SLLIW, ssa.OpRISCV64SRAI, ssa.OpRISCV64SRAIW,
 		ssa.OpRISCV64SRLI, ssa.OpRISCV64SRLIW, ssa.OpRISCV64SLTI, ssa.OpRISCV64SLTIU,
-		ssa.OpRISCV64RORI, ssa.OpRISCV64RORIW:
+		ssa.OpRISCV64RORI, ssa.OpRISCV64RORIW, ssa.OpRISCV64SLLIUW:
 		p := s.Prog(v.Op.Asm())
 		p.From.Type = obj.TYPE_CONST
 		p.From.Offset = v.AuxInt

src/cmd/compile/internal/ssa/_gen/RISCV64.rules

@@ -838,10 +838,14 @@
 // Optimisations for rva22u64 and above.
 //
 
+// Combine truncate and logic shift left. 
+(SLLI [i] (MOVWUreg x)) && i < 64 && buildcfg.GORISCV64 >= 22 => (SLLIUW [i] x)
+
 // Combine left shift and addition.
-(ADD (SLLI [1] x) y) && buildcfg.GORISCV64 >= 22 => (SH1ADD x y)
-(ADD (SLLI [2] x) y) && buildcfg.GORISCV64 >= 22 => (SH2ADD x y)
-(ADD (SLLI [3] x) y) && buildcfg.GORISCV64 >= 22 => (SH3ADD x y)
+(ADD (MOVWUreg x) y) && buildcfg.GORISCV64 >= 22 => (ADDUW x y)
+(ADD (SLLIUW [1] x) y) && buildcfg.GORISCV64 >= 22 => (SH1ADDUW x y)
+(ADD (SLLIUW [2] x) y) && buildcfg.GORISCV64 >= 22 => (SH2ADDUW x y)
+(ADD (SLLIUW [3] x) y) && buildcfg.GORISCV64 >= 22 => (SH3ADDUW x y)
 
 // Integer minimum and maximum.
 (Min64  x y) && buildcfg.GORISCV64 >= 22 => (MIN  x y)

src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

@@ -151,6 +151,7 @@ func init() {
 		{name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true}, // arg0 + arg1
 		{name: "ADDI", argLength: 1, reg: gp11sb, asm: "ADDI", aux: "Int64"},  // arg0 + auxint
 		{name: "ADDIW", argLength: 1, reg: gp11, asm: "ADDIW", aux: "Int64"},  // 32 low bits of arg0 + auxint, sign extended to 64 bits
+		{name: "ADDUW", argLength: 2, reg: gp21, asm: "ADDUW"},                // add least significant word of arg0 to arg1
 		{name: "NEG", argLength: 1, reg: gp11, asm: "NEG"},                    // -arg0
 		{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"},                  // -arg0 of 32 bits, sign extended to 64 bits
 		{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"},                    // arg0 - arg1
@@ -222,6 +223,7 @@ func init() {
 		{name: "SRLW", argLength: 2, reg: gp21, asm: "SRLW"},                 // arg0 >> (aux1 & 31), logical right shift of 32 bit value, sign extended to 64 bits
 		{name: "SLLI", argLength: 1, reg: gp11, asm: "SLLI", aux: "Int64"},   // arg0 << auxint, shift amount 0-63, logical left shift
 		{name: "SLLIW", argLength: 1, reg: gp11, asm: "SLLIW", aux: "Int64"}, // arg0 << auxint, shift amount 0-31, logical left shift of 32 bit value, sign extended to 64 bits
+		{name: "SLLIUW", argLength: 1, reg: gp11, asm: "SLLIUW", aux: "Int64"}, // arg0 << auxint, shift amount 0-31, logical left shift of 32 bit value, zero extended to 64 bits
 		{name: "SRAI", argLength: 1, reg: gp11, asm: "SRAI", aux: "Int64"},   // arg0 >> auxint, shift amount 0-63, arithmetic right shift
 		{name: "SRAIW", argLength: 1, reg: gp11, asm: "SRAIW", aux: "Int64"}, // arg0 >> auxint, shift amount 0-31, arithmetic right shift of 32 bit value, sign extended to 64 bits
 		{name: "SRLI", argLength: 1, reg: gp11, asm: "SRLI", aux: "Int64"},   // arg0 >> auxint, shift amount 0-63, logical right shift
@@ -231,6 +233,9 @@ func init() {
 		{name: "SH1ADD", argLength: 2, reg: gp21, asm: "SH1ADD"}, // arg0 << 1 + arg1
 		{name: "SH2ADD", argLength: 2, reg: gp21, asm: "SH2ADD"}, // arg0 << 2 + arg1
 		{name: "SH3ADD", argLength: 2, reg: gp21, asm: "SH3ADD"}, // arg0 << 3 + arg1
+		{name: "SH1ADDUW", argLength: 2, reg: gp21, asm: "SH1ADDUW"}, // shift the least significant word of arg0 left by 1 and add it to arg1
+		{name: "SH2ADDUW", argLength: 2, reg: gp21, asm: "SH2ADDUW"}, // shift the least significant word of arg0 left by 2 and add it to arg1
+		{name: "SH3ADDUW", argLength: 2, reg: gp21, asm: "SH3ADDUW"}, // shift the least significant word of arg0 left by 3 and add it to arg1
 
 		// Bitwise ops
 		{name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},   // arg0 & arg1

src/cmd/compile/internal/ssa/_gen/RISCV64latelower.rules

@@ -23,3 +23,8 @@
 (SRAI [0] x) => x
 (SRLI [0] x) => x
 (SLLI [0] x) => x
+
+// Combine left shift and addition.
+(ADD (SLLI [1] x) y) && buildcfg.GORISCV64 >= 22 => (SH1ADD x y)
+(ADD (SLLI [2] x) y) && buildcfg.GORISCV64 >= 22 => (SH2ADD x y)
+(ADD (SLLI [3] x) y) && buildcfg.GORISCV64 >= 22 => (SH3ADD x y)

src/cmd/compile/internal/ssa/opGen.go

@@ -220,6 +220,12 @@ func NegToInt32(a int) int {
 	return r
 }
 
+func AddWithLeastSignificantWord(a uint64, b int64) uint64 {
+	// riscv64/rva20u64:"MOVWU" "ADD"
+	// riscv64/rva22u64,riscv64/rva23u64:"ADDUW"
+	return a + uint64(uint32(b))
+}
+
 // -------------------- //
 //    Multiplication    //
 // -------------------- //