Labels

• blocker

  Something isn't working and no workaround
• deferred

  Deferred until after current Redesign Project
• dependencies

  Pull requests that update a dependency file
• documentation

  Improvements or additions to documentation
• duplicate

  This issue or pull request already exists
• ECO

  Engineering change order (post-PnR)
• enhancement

  New feature or request
• error

  Something isn't working
• flow

  Makefile or in-repository flow script changed
• good first issue

  Good for newcomers
• help wanted

  Extra attention is needed
• invalid

  This doesn't seem right
• packaging
• PnR

  Gate level verilog and/or layout changed
• precheck

  Issues related to precheck
• question

  Further information is requested
• RTL

  Verilog source code changed
• SDC

  Added or changed timing files
• signoff
• simulation

  Verilog testbenches and simulation
• wontfix

  This will not be worked on
• wrong repo

  Error is in a different repository