Changed decap_12/fill8/fill4 cell references break downstream full-chip STA (`make caravel-sta`)

[amm-efabless]

Some gate-level netlists in verilog/gl/ were changed after deletion of excessive decap_12 cells, but the way the files were rewritten to use Verilog instance arrays is not fully compatible with the caravel_user_project (and other) full-chip STA flows.

For more information, see: efabless/caravel_user_project#377