diff --git a/hdl/rtl/bus_wrapper/EF_PSRAM_CTRL_AHBL.v b/hdl/rtl/bus_wrapper/EF_PSRAM_CTRL_AHBL.v
index 4375079..5ee107e 100644
--- a/hdl/rtl/bus_wrapper/EF_PSRAM_CTRL_AHBL.v
+++ b/hdl/rtl/bus_wrapper/EF_PSRAM_CTRL_AHBL.v
@@ -181,7 +181,7 @@ module EF_PSRAM_CTRL_AHBL #(parameter REGISTER_HWDATA = 1)
     always@(posedge HCLK or negedge HRESETn) begin 
         if(!HRESETn) 
             last_HSIZE <= 0;
-        else if (HTRANS[1])
+        else if (HTRANS[1] & HREADYOUT)
                 last_HSIZE<=HSIZE;
     end
 
@@ -254,7 +254,7 @@ module EF_PSRAM_CTRL_AHBL #(parameter REGISTER_HWDATA = 1)
         else
             case (state)
                 ST_IDLE :   
-                    if((last_ahb_addr_phase|ahb_addr_phase) & data_cfg) 
+                    if((last_ahb_addr_phase|ahb_addr_phase)) 
                         HREADYOUT <= 1'b0;
                     else 
                         HREADYOUT <= 1'b1;
diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile
index 1e9a881..1e39bb2 100644
--- a/verify/uvm-python/Makefile
+++ b/verify/uvm-python/Makefile
@@ -10,7 +10,7 @@ VERILOG_SOURCES ?=  $(PWD)/top.v $(AHB_FILES) $(HDL_FILES) $(VIP_FILES)
 RTL_MACROS += "" # Add macros needed
 BUS_TYPE ?= AHB
 RTL_MACROS += -DBUS_TYPE_AHB
-DESIGN_NAME = EF_PSRAM_CTRL_ahbl
+DESIGN_NAME = EF_PSRAM_CTRL_AHBL
 export CLK_MAKEFILE = HCLK
 export RST_MAKEFILE = HRESETn
 ## netlist Gen