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Verilog: elaboration per compilation unit
IEEE 1800 2017 3.12.1 requires compliant tools to compile "compilation units" separately, with a compilation unit scope. This breaks out a function that elaborates a compilation unit by itself.
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5 files changed

+69
-22
lines changed

5 files changed

+69
-22
lines changed

src/verilog/Makefile

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@@ -6,6 +6,7 @@ SRC = aval_bval_encoding.cpp \
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verilog_bits.cpp \
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verilog_ebmc_language.cpp \
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verilog_elaborate.cpp \
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verilog_elaborate_compilation_unit.cpp \
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verilog_elaborate_module_instances.cpp \
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verilog_elaborate_type.cpp \
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verilog_expr.cpp \

src/verilog/verilog_ebmc_language.cpp

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@@ -22,6 +22,7 @@ Author: Daniel Kroening, dkr@amazon.com
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#include <langapi/language_util.h>
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#include <trans-word-level/show_module_hierarchy.h>
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#include "verilog_elaborate_compilation_unit.h"
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#include "verilog_language.h"
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#include "verilog_parser.h"
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#include "verilog_preprocessor.h"
@@ -412,25 +413,16 @@ show_modules(const verilog_ebmc_languaget::parse_treest &parse_trees)
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return result;
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}
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void verilog_ebmc_languaget::copy_parse_tree(
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const parse_treet &parse_tree,
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symbol_tablet &dest)
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symbol_tablet verilog_ebmc_languaget::elaborate_compilation_units(
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const parse_treest &parse_trees)
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{
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for(auto &item : parse_tree.items)
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{
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if(item.id() == ID_verilog_module || item.id() == ID_verilog_checker)
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{
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auto identifier =
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verilog_module_symbol(to_verilog_module_source(item).base_name());
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copy_module_source(item, identifier, dest);
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}
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else if(item.id() == ID_verilog_package)
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{
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auto identifier =
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verilog_package_identifier(to_verilog_module_source(item).base_name());
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copy_module_source(item, identifier, dest);
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}
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}
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symbol_tablet symbol_table;
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for(auto &parse_tree : parse_trees)
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verilog_elaborate_compilation_unit(
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parse_tree, symbol_table, message_handler);
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return symbol_table;
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}
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std::optional<transition_systemt> verilog_ebmc_languaget::transition_system()
@@ -481,10 +473,7 @@ std::optional<transition_systemt> verilog_ebmc_languaget::transition_system()
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//
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// copy the parse trees into the symbol table
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//
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symbol_tablet symbol_table;
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for(auto &parse_tree : parse_trees)
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copy_parse_tree(parse_tree, symbol_table);
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symbol_tablet symbol_table = elaborate_compilation_units(parse_trees);
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//
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// type checking

src/verilog/verilog_ebmc_language.h

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@@ -67,6 +67,7 @@ class verilog_ebmc_languaget : public ebmc_languaget
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std::map<irep_idt, modulet> module_map;
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symbol_tablet elaborate_compilation_units(const parse_treest &);
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transition_systemt typecheck(const parse_treest &, symbol_tablet &&);
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void typecheck_module(modulet &, symbol_tablet &);
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};
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/*******************************************************************\
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Module: Elaboration of Verilog Compilation Units
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Author: Daniel Kroening, dkr@amazon.com
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\*******************************************************************/
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#include "verilog_elaborate_compilation_unit.h"
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#include "verilog_typecheck.h"
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void verilog_elaborate_compilation_unit(
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const verilog_parse_treet &parse_tree,
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symbol_table_baset &symbol_table,
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message_handlert &message_handler)
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{
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for(auto &item : parse_tree.items)
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{
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if(item.id() == ID_verilog_module || item.id() == ID_verilog_checker)
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{
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auto identifier =
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verilog_module_symbol(to_verilog_module_source(item).base_name());
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copy_module_source(item, identifier, symbol_table);
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}
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else if(item.id() == ID_verilog_package)
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{
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auto identifier =
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verilog_package_identifier(to_verilog_module_source(item).base_name());
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copy_module_source(item, identifier, symbol_table);
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}
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}
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}
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/*******************************************************************\
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Module: Elaboration of Verilog Compilation Units
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Author: Daniel Kroening, dkr@amazon.com
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\*******************************************************************/
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#ifndef CPROVER_VERILOG_ELABORATE_COMPILATION_UNIT_H
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#define CPROVER_VERILOG_ELABORATE_COMPILATION_UNIT_H
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#include <util/message.h>
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#include <util/symbol_table_base.h>
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#include "verilog_parse_tree.h"
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/// throws ebmc_errort on failure
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void verilog_elaborate_compilation_unit(
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const verilog_parse_treet &,
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symbol_table_baset &,
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message_handlert &);
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#endif // CPROVER_VERILOG_ELABORATE_UNIT_H

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