Commit 05114a9
Bruce Ashfield
isospec: process all destinations in design cells
It is possible that valid destinations for devices are more
than one level deep in the design cells. Instead of only
processing immediate children, we process all subnodes of
the design instead.
Note: this could be restricted to specific types of cells
in the future (i.e. "ps") or triggered on cells that
indicate they have subnodes. But for now, this approach
ensures that we don't miss collecting any possible devices.
Signed-off-by: Bruce Ashfield <bruce.ashfield@amd.com>1 parent 2b936c7 commit 05114a9
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