[Intel/Haswell/Desktop] Core i5-4570 IMC Timings and DIMM geometry

[cyring]

i5-4570

Timings

Setting	CoreFreq	BIOS
tRRD	5	4
tWR	N/A	10
tFAW	N/A	20
tRTP	N/A	5
tWTP	N/A	21
drWR	4	5
tCKE	N/A	4

Geometry

( 8 x Bank x Rank x Rows x Cols ) / ( 1024 x 1024 )

( 8 x 8 x 2 x 16384 x 1024 ) / ( 1024 x 1024) = 2048 MB vs 8192 MB

Originally posted by @cyring in #342 (reply in thread)

[cyring]

@svmlegacy and any Broadwell, Haswell owner:

I need to dump Register at MCHBAR address 0x4c00
(This register is undocumented, so we are reversing in this header file)

Based on develop branch, in function HSW_IMC(), add the following printf to dump the register value.

CoreFreq/corefreqd.c

Line 3824 in 2fe50f3

for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++)

    for (cha = 0; cha < RO(Shm)->Uncore.MC[mc].ChannelCount; cha++)
    {
	printf( "Cha(%d) REG4C00[%x]\n", cha,
		RO(Proc)->Uncore.MC[mc].Channel[cha].HSW.REG4C00.value );

Please post the output of corefreqd here, bellow:

[cyring]

@svmlegacy : For IMC testing, here's a Haswell/Broadwell development archive.

CoreFreq_develop.tar.gz

[cyring]

@svmlegacy Hello,

Changes are now tracked through a dedicated Haswell, Broadwell branch

You just have to pull and build develop_HSW_BDW to test the IMC

Thank you

[svmlegacy]

Intel Core i5-4570

Develop branch:

develop_HSW_BDW branch:

[cyring]

develop_HSW_BDW branch:

Thank you.

Can you pull and test develop_HSW_BDW in which I'm trying to better estimate the DIMM slots count.

[svmlegacy]

Motherboard is a Gigabyte GA-Z97-HD3P Rev. 1.0 Four DIMM slots available, slots "3" & "4" populated (Closest and 3rd closest to CPU socket)

[cyring]

Motherboard is a Gigabyte GA-Z97-HD3P Rev. 1.0 Four DIMM slots available, slots "3" & "4" populated (Closest and 3rd closest to CPU socket)

If dual channel set, topology looks OK but what is wrong is the number of rows: it should be 65536 instead of 16384

[cyring]

@svmlegacy Can you please pull and test the develop branch ?

DIMM rows count is now computed using a formula made for Skylake.

[cyring]

@svmlegacy Can you please pull and test the develop branch ?

DIMM rows count is now computed using a formula made for Skylake.

@svmlegacy could you please test Haswell IMC from latest develop ?

[svmlegacy]

Fresh pull from Develop: