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mkalkbrennerPastorL69
mkalkbrenner
and
PastorL69
authored
fixed SAM and Whitestar errors (#6)
* fixed SAM and Whitestar errors * be consistent * use constants * fixed pixel counts --------- Co-authored-by: pastor <[email protected]>
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6 files changed

+122
-133
lines changed

6 files changed

+122
-133
lines changed

‎src/dmd_interface_desega.pio‎

Lines changed: 27 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -5,65 +5,51 @@
55
.define DOTCLK 3
66
.define SDATA 2
77

8+
.define FRAME_START_IRQ 4
89

9-
.program dmd_reader_desega
10+
.define PUBLIC desega_DE DE
11+
.define PUBLIC desega_RDATA RDATA
12+
.define PUBLIC desega_DOTCLK DOTCLK
13+
.define PUBLIC desega_SDATA SDATA
1014

11-
; Send using an external clock on the SPI interface
1215

13-
; initialize y with 4096 = number of pixels (128x32)
14-
set x, 1
15-
in x, 1
16-
in null, 13
17-
mov y, isr
16+
.program dmd_reader_desega
17+
; initialize y with 8191, number of pixels ((128 x LSB + 128 x MSB) x 32) - 1 because counting starts at 0.
18+
set x, 31 ; x = 31 (max 5-bit value)
19+
in x, 5 ; shift in 5 bits, isr = 31
20+
set x, 31 ; x = 31
21+
in x, 5 ; shift in 5 bits, isr = 1023
22+
set x, 15 ; x = 15
23+
in x, 3 ; shift in 3 bits, isr = 8191
24+
mov y, isr ; y = 8191
1825

1926
.wrap_target
2027

2128
mov x, y ; load number of pixels
2229
mov isr, null ; reset shift counter
2330

24-
irq clear 4
25-
wait irq 4
31+
irq clear FRAME_START_IRQ
32+
wait irq FRAME_START_IRQ
2633

27-
28-
; this is the loop for the most significant bit
29-
dotloop1:
34+
dotloop:
3035
wait 0 gpio DOTCLK ; falling edge
31-
wait 1 gpio DOTCLK ; raising edge
32-
in pins 1 ; read pin data
33-
in null 1 ; right padding
34-
jmp x-- dotloop1
35-
36-
mov x, y ; load number of pixels
37-
mov isr, null ; reset shift counter
38-
39-
; There's an empty line between LSB and HSB plane
40-
wait 0 gpio RCLK
41-
wait 1 gpio RCLK
42-
43-
; this is the loop for the least significant bit
44-
; in this loop, the bit value is multipled by 2 by shifting it one bit
45-
dotloop2:
46-
wait 0 gpio DOTCLK ; falling edge
47-
wait 1 gpio DOTCLK ; raising edge
4836
in null 1 ; left padding
37+
wait 1 gpio DOTCLK ; raising edge
4938
in pins 1 ; read pin data
50-
jmp x-- dotloop2
51-
39+
jmp x-- dotloop
5240

5341
.wrap
5442

5543

5644
.program dmd_framedetect_desega
57-
5845
.wrap_target
5946

6047
; Data East/Sega frame start detection
6148
; ~7.86µs is the longest state in which DE can be low without it being a new frame
62-
; Each nop [31] = 32 cycles = 256 ns @125 MHz
6349
; We go with 10 µs to be safe and confirm the start of a new frame, which is 256ns * 39 = 9.98 µs
50+
6451
wait_low:
6552
wait 0 gpio DE ; Wait for DE to go low
66-
6753
set x, 20 ; Use x as storage for 20 iterations
6854

6955
delay_loop:
@@ -73,7 +59,7 @@ delay_loop:
7359

7460
; After ~10 µs, check if still low
7561
jmp pin, wait_low ; If pin went high early → back to wait_low
76-
irq 4 ; Pin remained low long enough → trigger IRQ
62+
irq FRAME_START_IRQ ; Pin remained low long enough → frame started
7763

7864
wait 1 gpio DE ; Wait again for it to go high before restarting cycle
7965
jmp wait_low ; went high, time to go back to wait_low
@@ -86,16 +72,14 @@ static inline void dmd_reader_desega_program_init(PIO pio, uint sm, uint offset)
8672
pio_sm_config c = dmd_reader_desega_program_get_default_config(offset);
8773

8874
// Set the IN pin, we don't use any other
89-
sm_config_set_in_pins(&c, 2); // SDATA
75+
sm_config_set_in_pins(&c, desega_SDATA);
9076

9177
// Set the pin direction at the PIO
92-
pio_sm_set_consecutive_pindirs(pio, sm, 5, 1, false); // RCLK
93-
pio_sm_set_consecutive_pindirs(pio, sm, 2, 2, false); // SDATA, DOTCLK
78+
pio_sm_set_consecutive_pindirs(pio, sm, desega_SDATA, 2, false); // SDATA, DOTCLK
9479

9580
// Connect these GPIOs to this PIO block
96-
pio_gpio_init(pio, 5); // RCLK
97-
pio_gpio_init(pio, 3); // DOTCLK
98-
pio_gpio_init(pio, 2); // SDATA
81+
pio_gpio_init(pio, desega_DOTCLK);
82+
pio_gpio_init(pio, desega_SDATA);
9983

10084
// Shifting to left matches the customary MSB-first ordering of SPI.
10185
sm_config_set_in_shift(
@@ -118,10 +102,10 @@ static inline void dmd_framedetect_desega_program_init(PIO pio, uint sm, uint of
118102
pio_sm_config c = dmd_framedetect_desega_program_get_default_config(offset);
119103

120104
// Set the pin direction at the PIO
121-
pio_sm_set_consecutive_pindirs(pio, sm, 7, 1, false); // DE
105+
pio_sm_set_consecutive_pindirs(pio, sm, desega_DE, 1, false);
122106

123107
// Connect this GPIO to this PIO block
124-
pio_gpio_init(pio, 7); // DE
108+
pio_gpio_init(pio, desega_DE);
125109

126110
// Load our configuration, do not yet start the program
127111
pio_sm_init(pio, sm, offset, &c);

‎src/dmd_interface_sam.pio‎

Lines changed: 27 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -5,46 +5,44 @@
55
.define DOTCLK 3
66
.define SDATA 2
77

8+
.define FRAME_START_IRQ 4
89

9-
.program dmd_reader_sam
10-
11-
; Send using an external clock on the SPI interface
12-
; - IN pin 0 is the DATA pin
10+
.define PUBLIC sam_RCLK RCLK
11+
.define PUBLIC sam_RDATA RDATA
12+
.define PUBLIC sam_DOTCLK DOTCLK
13+
.define PUBLIC sam_SDATA SDATA
1314

14-
; initialize y with 16348 = number of pixels (128x32x4)
15-
set x, 1
16-
in x, 1
17-
in null, 15
18-
mov y, isr
15+
.program dmd_reader_sam
16+
; initialize y with 16383, number of pixels (128x32x4) - 1 because counting starts at 0.
17+
set x, 31 ; x = 31 (max 5-bit value)
18+
in x, 5 ; shift in 5 bits, isr = 31
19+
set x, 31 ; x = 31
20+
in x, 5 ; shift in 5 bits, isr = 1023
21+
set x, 15 ; x = 15
22+
in x, 4 ; shift in 4 bits, isr = 16383
23+
mov y, isr ; y = 16383
1924

2025
.wrap_target
21-
2226
mov x, y ; load number of pixels
2327
mov isr, null ; reset shift counter
2428

25-
irq clear 4
26-
wait irq 4
29+
irq clear FRAME_START_IRQ
30+
wait irq FRAME_START_IRQ
2731

2832
dotloop:
2933
wait 0 gpio DOTCLK ; falling edge
30-
in null, 3 ; pad with 3 zeros
34+
in null, 3 ; left padding with 3 zeros
3135
wait 1 gpio DOTCLK ; raising edge
3236
in pins 1 ; read pin data
33-
34-
3537
jmp x-- dotloop
36-
3738
.wrap
3839

39-
.program dmd_framedetect_sam
4040

41+
.program dmd_framedetect_sam
4142
.wrap_target
42-
43-
; synchronize on the least significant plane
4443
wait 0 gpio RDATA
4544
wait 1 gpio RDATA
46-
irq 4
47-
45+
irq FRAME_START_IRQ
4846
.wrap
4947

5048

@@ -53,14 +51,14 @@ static inline void dmd_reader_sam_program_init(PIO pio, uint sm, uint offset) {
5351
pio_sm_config c = dmd_reader_sam_program_get_default_config(offset);
5452

5553
// Set the IN pin, we don't use any other
56-
sm_config_set_in_pins(&c, 2); // SDATA
57-
58-
// Connect these GPIOs to this PIO block
59-
pio_gpio_init(pio, 3); // DOTCLK
60-
pio_gpio_init(pio, 2); // SDATA
54+
sm_config_set_in_pins(&c, sam_SDATA);
6155

6256
// Set the pin direction at the PIO
63-
pio_sm_set_consecutive_pindirs(pio, sm, 2, 2, false); // SDATA, DOTCLK
57+
pio_sm_set_consecutive_pindirs(pio, sm, sam_SDATA, 2, false); // SDATA, DOTCLK
58+
59+
// Connect these GPIOs to this PIO block
60+
pio_gpio_init(pio, sam_DOTCLK);
61+
pio_gpio_init(pio, sam_SDATA);
6462

6563
// Shifting to left matches the customary MSB-first ordering of SPI.
6664
sm_config_set_in_shift(
@@ -83,10 +81,10 @@ static inline void dmd_framedetect_sam_program_init(PIO pio, uint sm, uint offse
8381
pio_sm_config c = dmd_framedetect_sam_program_get_default_config(offset);
8482

8583
// Set the pin direction at the PIO
86-
pio_sm_set_consecutive_pindirs(pio, sm, 6, 1, false); // RDATA
84+
pio_sm_set_consecutive_pindirs(pio, sm, sam_RDATA, 1, false);
8785

8886
// Connect these GPIOs to this PIO block
89-
pio_gpio_init(pio, 6); // RDATA
87+
pio_gpio_init(pio, sam_RDATA);
9088

9189
// Load our configuration, do not yet start the program
9290
pio_sm_init(pio, sm, offset, &c);

‎src/dmd_interface_spike.pio‎

Lines changed: 17 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,12 @@
55
.define DOTCLK 3
66
.define SDATA 2
77

8+
.define PLANE_START_IRQ 4
89

9-
.define PUBLIC spike_rdata RDATA
10+
.define PUBLIC spike_RCLK RCLK
11+
.define PUBLIC spike_RDATA RDATA
12+
.define PUBLIC spike_DOTCLK DOTCLK
13+
.define PUBLIC spike_SDATA SDATA
1014

1115

1216
.program dmd_reader_spike
@@ -22,8 +26,8 @@
2226
mov x, y ; load number of pixels
2327
mov isr, null ; reset shift counter
2428

25-
irq clear 4
26-
wait irq 4
29+
irq clear PLANE_START_IRQ
30+
wait irq PLANE_START_IRQ
2731

2832
; this is the loop for the most significant bit
2933
dotloop1:
@@ -77,7 +81,7 @@ lineloop:
7781
wait 0 gpio RCLK
7882
jmp x-- lineloop
7983

80-
irq 4
84+
irq PLANE_START_IRQ
8185

8286
.wrap
8387

@@ -86,14 +90,13 @@ static inline void dmd_reader_spike_program_init(PIO pio, uint sm, uint offset)
8690
pio_sm_config c = dmd_reader_spike_program_get_default_config(offset);
8791

8892
// Set the IN base pin to the provided `pin` parameter. This is the data pin, we don't use any other
89-
sm_config_set_in_pins(&c, 2); // SDATA
90-
93+
sm_config_set_in_pins(&c, spike_SDATA);
9194
// Set the pin direction at the PIO
92-
pio_sm_set_consecutive_pindirs(pio, sm, 2, 2, false); // SDATA, DOTCLK
95+
pio_sm_set_consecutive_pindirs(pio, sm, spike_SDATA, 2, false); // SDATA, DOTCLK
9396

9497
// Connect these GPIOs to this PIO block
95-
pio_gpio_init(pio, 3); // DOTCLK
96-
pio_gpio_init(pio, 2); // SDATA
98+
pio_gpio_init(pio, spike_DOTCLK);
99+
pio_gpio_init(pio, spike_SDATA);
97100

98101
// Shifting to left matches the customary MSB-first ordering of SPI.
99102
sm_config_set_in_shift(
@@ -114,8 +117,8 @@ static inline void dmd_reader_spike_program_init(PIO pio, uint sm, uint offset)
114117
% c-sdk {
115118
static inline void dmd_framedetect_spike_program_init(PIO pio, uint sm, uint offset) {
116119
pio_sm_config c = dmd_framedetect_spike_program_get_default_config(offset);
117-
// rdata is used for jump control
118-
sm_config_set_jmp_pin(&c, spike_rdata);
120+
// RDATA is used for jump control
121+
sm_config_set_jmp_pin(&c, spike_RDATA);
119122

120123
// Shifting to left matches the customary MSB-first ordering of SPI.
121124
sm_config_set_in_shift(
@@ -126,11 +129,11 @@ static inline void dmd_framedetect_spike_program_init(PIO pio, uint sm, uint off
126129
);
127130

128131
// Set the pin direction at the PIO
129-
pio_sm_set_consecutive_pindirs(pio, sm, 5, 2, false); // RCLK, RDATA
132+
pio_sm_set_consecutive_pindirs(pio, sm, spike_RCLK, 2, false); // RCLK, RDATA
130133

131134
// Connect these GPIOs to this PIO block
132-
pio_gpio_init(pio, 6); // RDATA
133-
pio_gpio_init(pio, 5); // RCLK
135+
pio_gpio_init(pio, spike_RDATA);
136+
pio_gpio_init(pio, spike_RCLK);
134137

135138
// Load our configuration, do not yet start the program
136139
pio_sm_init(pio, sm, offset, &c);

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