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split c from asm code
1 parent 97d5d25 commit 6c656a4

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2 files changed

+60
-7
lines changed

2 files changed

+60
-7
lines changed

src/dmd_interface_desega.h

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@@ -0,0 +1,53 @@
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#ifndef DMD_INTERFACE_DESEGA_H
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#define DMD_INTERFACE_DESEGA_H
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#include "dmd_interface_desega.pio.h"
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#include "hardware/gpio.h"
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#include "hardware/pio.h"
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static inline void dmd_reader_desega_program_init(PIO pio, uint sm,
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uint offset) {
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pio_sm_config c = dmd_reader_desega_program_get_default_config(offset);
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// Set the IN pin, we don't use any other
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sm_config_set_in_pins(&c, desega_SDATA);
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// Set the pin direction at the PIO
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pio_sm_set_consecutive_pindirs(pio, sm, desega_SDATA, 2,
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false); // SDATA, DOTCLK
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// Connect these GPIOs to this PIO block
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pio_gpio_init(pio, desega_DOTCLK);
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pio_gpio_init(pio, desega_SDATA);
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// Shifting to left matches the customary MSB-first ordering of SPI.
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sm_config_set_in_shift(&c,
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false, // Shift-to-right = false
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true, // Autopull enabled
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32 // Autopull threshold
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);
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// We only send, so disable the TX FIFO to make the RX FIFO deeper.
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sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
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// Load our configuration, do not yet start the program
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pio_sm_init(pio, sm, offset, &c);
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}
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static inline void dmd_framedetect_desega_program_init(PIO pio, uint sm,
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uint offset) {
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pio_sm_config c = dmd_framedetect_desega_program_get_default_config(offset);
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// DE is used for jump control
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sm_config_set_jmp_pin(&c, desega_DE);
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// Set the pin direction at the PIO
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pio_sm_set_consecutive_pindirs(pio, sm, desega_DE, 1, false);
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// Connect this GPIO to this PIO block
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pio_gpio_init(pio, desega_DE);
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// Load our configuration, do not yet start the program
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pio_sm_init(pio, sm, offset, &c);
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}
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#endif // DMD_INTERFACE_DESEGA_H

src/dmd_interface_spike.pio

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -41,13 +41,13 @@ dotloop:
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.program dmd_framedetect_spike
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; Frame detection in Spike:
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; white for RDATA to go H
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; check if it is still H 150-250ms later - in this case, this is the most significant bit
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; which is the last plane
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; now wait for RDATA to go L and H again, this is the beginning of a new frame
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; based on 125MHz clock frequency we have to wait 18750-31250 clock cycles
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; we use 24576 here, because it0s 0b11 << 13
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; Frame detection in Spike:
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; white for RDATA to go H
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; check if it is still H 150-250ms later - in this case, this is the most significant bit
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; which is the last plane
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; now wait for RDATA to go L and H again, this is the beginning of a new frame
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; based on 125MHz clock frequency we have to wait 18750-31250 clock cycles
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; we use 24576 here, because it0s 0b11 << 13
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; initialize isr with 24576
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set x, 3

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