From 1a8decabf8f5cf64e2f4863c2851410f7f06d76f Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Tue, 18 Oct 2022 13:16:50 -0300 Subject: [PATCH 01/22] ppc64: initialize ri->prev_insn --- risu_reginfo_ppc64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 9899b36..89d5db3 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -49,6 +49,7 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) memset(ri, 0, sizeof(*ri)); ri->faulting_insn = *((uint32_t *) uc->uc_mcontext.regs->nip); + ri->prev_insn = *((uint32_t *) (uc->uc_mcontext.regs->nip - 4)); ri->nip = uc->uc_mcontext.regs->nip - image_start_address; for (i = 0; i < NGREG; i++) { From 9a4afd2328c56e1b7f3601baa52b0d5d2689da57 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Mon, 24 Oct 2022 14:53:55 -0300 Subject: [PATCH 02/22] ppc64: use 32-bits values for each VR word --- risugen_ppc64.pm | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index b241172..f5c0997 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -136,7 +136,7 @@ sub write_random_ppc64_vrdata() { for (my $i = 0; $i < 32; $i++) { # load a random doubleword value at r0 - write_mov_ri128(rand(0xffff), rand(0xffff), rand(0xfffff), rand(0xfffff)); + write_mov_ri128(rand(0xffffffff), rand(0xffffffff), rand(0xffffffff), rand(0xffffffff)); # li r0, 16 write_mov_ri16(0, 0x10); # lvx vr$i, r1, r0 From 38a1b958df29cc9a1c9588287b7402eb3b997808 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Mon, 7 Mar 2022 16:20:08 -0300 Subject: [PATCH 03/22] ppc64: init and compare whole ccr --- risu_reginfo_ppc64.c | 2 +- risugen_ppc64.pm | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 89d5db3..7445832 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -83,7 +83,7 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a) return 0; } - if ((m->gregs[CCR] & 0x10) != (a->gregs[CCR] & 0x10)) { + if ((m->gregs[CCR]) != (a->gregs[CCR])) { return 0; } diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index f5c0997..9c0bf8c 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -170,6 +170,9 @@ sub clear_vr_registers() # zero the xer register # mtxer r23 insn32(0x7ee103a6); + # zero the ccr register + # mtcrf 0xff,r23 + insn32(0x7eeff120); # std r23, 0(r22) insn32(0xfaf60000); From 91e86981b6bd54c34c6b9406d33934cad52059c2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Mon, 20 Dec 2021 11:13:43 -0300 Subject: [PATCH 04/22] ppc64: Add fpscr comparison MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Víctor Colombo [ferst: Ignore FPSCR[FR] for now; Rebase; ] --- risu_reginfo_ppc64.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 7445832..9f31b1a 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -57,7 +57,8 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) } memcpy(ri->fpregs, uc->uc_mcontext.fp_regs, 32 * sizeof(double)); - ri->fpscr = uc->uc_mcontext.fp_regs[32]; + memcpy(&ri->fpscr, &uc->uc_mcontext.fp_regs[32], sizeof(uint64_t)); + ri->fpscr &= ~0x40000; /* ignore FR bit */ memcpy(ri->vrregs.vrregs, uc->uc_mcontext.v_regs->vrregs, sizeof(ri->vrregs.vrregs[0]) * 32); @@ -93,6 +94,10 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a) } } + if (m->fpscr != a->fpscr) { + return 0; + } + for (i = 0; i < 32; i++) { if (m->vrregs.vrregs[i][0] != a->vrregs.vrregs[i][0] || m->vrregs.vrregs[i][1] != a->vrregs.vrregs[i][1] || @@ -181,6 +186,11 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f) } } + if (m->fpscr != a->fpscr) { + fprintf(f, "Mismatch: FPSCR\n"); + fprintf(f, "m: [0x%016lx] != a: [0x%016lx]\n", m->fpscr, a->fpscr); + } + for (i = 0; i < 32; i++) { if (m->vrregs.vrregs[i][0] != a->vrregs.vrregs[i][0] || m->vrregs.vrregs[i][1] != a->vrregs.vrregs[i][1] || From fe514ef7d54e0a604d3e950f24760b460846f4a8 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Tue, 18 Oct 2022 13:42:22 -0300 Subject: [PATCH 05/22] ppc64: initialize and compare CTR --- risu_reginfo_ppc64.c | 10 ++++++++++ risugen_ppc64.pm | 4 ++++ 2 files changed, 14 insertions(+) diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 9f31b1a..68b1d96 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -21,6 +21,7 @@ #include "risu.h" #include "risu_reginfo_ppc64.h" +#define CTR 35 #define XER 37 #define CCR 38 @@ -80,6 +81,10 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a) } } + if (m->gregs[CTR] != a->gregs[CTR]) { + return 0; + } + if (m->gregs[XER] != a->gregs[XER]) { return 0; } @@ -168,6 +173,11 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f) } } + if (m->gregs[CTR] != a->gregs[CTR]) { + fprintf(f, "Mismatch: CTR\n"); + fprintf(f, "m: [%lx] != a: [%lx]\n", m->gregs[CTR], a->gregs[CTR]); + } + if (m->gregs[XER] != a->gregs[XER]) { fprintf(f, "Mismatch: XER\n"); fprintf(f, "m: [%lx] != a: [%lx]\n", m->gregs[XER], a->gregs[XER]); diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index 9c0bf8c..21af070 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -159,6 +159,10 @@ sub write_random_regdata() } write_mov_ri($i, rand(0xffffffff)); } + + # Count register + write_mov_ri(0, rand(0xffffffff)); + insn32(0x7c0903a6); # mtctr r0 } sub clear_vr_registers() From a84390d74954f6bff170ddce130490e859e27f4b Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Tue, 18 Oct 2022 14:29:01 -0300 Subject: [PATCH 06/22] ppc64: initialize and compare VSCR and VRSAVE --- risu_reginfo_ppc64.c | 24 ++++++++++++++++++++++++ risugen_ppc64.pm | 8 ++++++++ 2 files changed, 32 insertions(+) diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 68b1d96..6138dee 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -111,6 +111,15 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a) return 0; } } + + if (m->vrregs.vscr.vscr_word != a->vrregs.vscr.vscr_word) { + return 0; + } + + if (m->vrregs.vrsave != a->vrregs.vrsave) { + return 0; + } + return 1; } @@ -154,6 +163,8 @@ int reginfo_dump(struct reginfo *ri, FILE * f) ri->vrregs.vrregs[i][0], ri->vrregs.vrregs[i][1], ri->vrregs.vrregs[i][2], ri->vrregs.vrregs[i][3]); } + fprintf(f, "\tvscr: %8x\tvrsave: %8x\n", ri->vrregs.vscr.vscr_word, + ri->vrregs.vrsave); return !ferror(f); } @@ -215,5 +226,18 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f) a->vrregs.vrregs[i][2], a->vrregs.vrregs[i][3]); } } + + if (m->vrregs.vscr.vscr_word != a->vrregs.vscr.vscr_word) { + fprintf(f, "Mismatch: VSCR\n"); + fprintf(f, "m: [%8x] != a: [%8x]\n", m->vrregs.vscr.vscr_word, + a->vrregs.vscr.vscr_word); + } + + if (m->vrregs.vrsave != a->vrregs.vrsave) { + fprintf(f, "Mismatch: VRSAVE\n"); + fprintf(f, "m: [%8x] != a: [%8x]\n", m->vrregs.vrsave, + a->vrregs.vrsave); + } + return !ferror(f); } diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index 21af070..0506878 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -134,6 +134,14 @@ sub write_random_ppc64_fpdata() sub write_random_ppc64_vrdata() { + # Vector Status and Control Register + insn32(0x100004c4); # vxor vr0, vr0, vr0 + insn32(0x10000644); # mtvscr vr0 + + # VR Save Register + write_mov_ri(0, rand(0xffffffff)); + insn32(0x7c0043a6); # mtvrsave r0 + for (my $i = 0; $i < 32; $i++) { # load a random doubleword value at r0 write_mov_ri128(rand(0xffffffff), rand(0xffffffff), rand(0xffffffff), rand(0xffffffff)); From d559cf5094a0922b1899ccaa313f773738acb64e Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Tue, 21 Dec 2021 11:53:07 -0300 Subject: [PATCH 07/22] ppc64: add VSX support. The current code can be used to test VSX instructions, but the lower half of the first 32 VSRs are ignored. Add risugen code to (conditionally) initialize the 128-bits of all VSX registers and C code to compare the lower 64-bits of VSRs 0-31. --- risu_reginfo_ppc64.c | 32 ++++++++++++++++++++++++++++++++ risu_reginfo_ppc64.h | 1 + risugen | 6 +++++- risugen_ppc64.pm | 44 ++++++++++++++++++++++++++++++++++++-------- 4 files changed, 74 insertions(+), 9 deletions(-) diff --git a/risu_reginfo_ppc64.c b/risu_reginfo_ppc64.c index 6138dee..31bfe1b 100644 --- a/risu_reginfo_ppc64.c +++ b/risu_reginfo_ppc64.c @@ -65,6 +65,17 @@ void reginfo_init(struct reginfo *ri, ucontext_t *uc) sizeof(ri->vrregs.vrregs[0]) * 32); ri->vrregs.vscr = uc->uc_mcontext.v_regs->vscr; ri->vrregs.vrsave = uc->uc_mcontext.v_regs->vrsave; + + for (i = 0; i < 32; i++) { + /* + * From sigcontext.h: + * "FPR/VSR 0-31 doubleword 0 is stored in fp_regs, and VMX/VSR 32-63 + * is stored at the start of vmx_reserve. vmx_reserve is extended for + * backwards compatility to store VSR 0-31 doubleword 1 after the VMX + * registers and vscr/vrsave." + */ + ri->vsrreghalf[i] = uc->uc_mcontext.vmx_reserve[2 * NVRREG + 1 + i]; + } } /* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ @@ -112,6 +123,12 @@ int reginfo_is_eq(struct reginfo *m, struct reginfo *a) } } + for (i = 0; i < 32; i++) { + if (m->vsrreghalf[i] != a->vsrreghalf[i]) { + return 0; + } + } + if (m->vrregs.vscr.vscr_word != a->vrregs.vscr.vscr_word) { return 0; } @@ -166,6 +183,11 @@ int reginfo_dump(struct reginfo *ri, FILE * f) fprintf(f, "\tvscr: %8x\tvrsave: %8x\n", ri->vrregs.vscr.vscr_word, ri->vrregs.vrsave); + for (i = 0; i < 32; i++) { + fprintf(f, "vsr%02d: %16lx, %16lx\n", i, ri->fpregs[i], + ri->vsrreghalf[i]); + } + return !ferror(f); } @@ -239,5 +261,15 @@ int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE *f) a->vrregs.vrsave); } + for (i = 0; i < 32; i++) { + if (m->vsrreghalf[i] != a->vsrreghalf[i]) { + fprintf(f, "Mismatch: Register vsr%d\n", i); + fprintf(f, "m: [%16lx, %16lx] != a: [%16lx, %16lx]\n", + m->fpregs[i], m->vsrreghalf[i], + a->fpregs[i], a->vsrreghalf[i]); + return 0; + } + } + return !ferror(f); } diff --git a/risu_reginfo_ppc64.h b/risu_reginfo_ppc64.h index 4b1d8bd..044fcd9 100644 --- a/risu_reginfo_ppc64.h +++ b/risu_reginfo_ppc64.h @@ -23,6 +23,7 @@ struct reginfo { uint64_t fpregs[32]; uint64_t fpscr; vrregset_t vrregs; + uint64_t vsrreghalf[32]; }; #endif /* RISU_REGINFO_PPC64LE_H */ diff --git a/risugen b/risugen index e690b18..586bb8f 100755 --- a/risugen +++ b/risugen @@ -310,6 +310,7 @@ Valid options: Useful to test before support for FP is available. --sve : enable sve floating point --be : generate instructions in Big-Endian byte order (ppc64 only). + --vsx : initialize vector-scalar extension facility registers with random data (ppc64 only). --help : print this message EOT } @@ -321,6 +322,7 @@ sub main() my $fpscr = 0; my $fp_enabled = 1; my $sve_enabled = 0; + my $vsx_enabled = 0; my $big_endian = 0; my ($infile, $outfile); @@ -337,6 +339,7 @@ sub main() } }, "be" => sub { $big_endian = 1; }, + "vsx" => sub { $vsx_enabled = 1; }, "no-fp" => sub { $fp_enabled = 0; }, "sve" => sub { $sve_enabled = 1; }, ) or return 1; @@ -372,7 +375,8 @@ sub main() 'keys' => \@insn_keys, 'arch' => $full_arch[0], 'subarch' => $full_arch[1] || '', - 'bigendian' => $big_endian + 'bigendian' => $big_endian, + 'vsx_enabled' => $vsx_enabled ); write_test_code(\%params); diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index 0506878..10b18f8 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -152,6 +152,29 @@ sub write_random_ppc64_vrdata() } } +sub write_random_ppc64_vsrdata() +{ + # Vector Status and Control Register + insn32(0x100004c4); # vxor vr0, vr0, vr0 + insn32(0x10000644); # mtvscr vr0 + + # VR Save Register + write_mov_ri(0, rand(0xffffffff)); + insn32(0x7c0043a6); # mtvrsave r0 + + for (my $i = 0; $i < 32; $i++) { + # load a random quadword value at r0 + write_mov_ri128(rand(0xffffffff), rand(0xffffffff), rand(0xffffffff), rand(0xffffffff)); + # lxv vsr[$i], 16(r1) + insn32((0x3d << 26) | ($i << 21) | (0x1 << 16) | (0x0 << 4) | 0x1); + + # load another random quadword value at r0 + write_mov_ri128(rand(0xffffffff), rand(0xffffffff), rand(0xffffffff), rand(0xffffffff)); + # lxv vsr[$i+32], 16(r1) + insn32((0x3d << 26) | ($i << 21) | (0x1 << 16) | (0x1 << 4) | 0x1); + } +} + sub write_random_regdata() { # clear condition register @@ -200,16 +223,20 @@ my $OP_SETMEMBLOCK = 2; # r0 is address of memory block (8192 bytes) my $OP_GETMEMBLOCK = 3; # add the address of memory block to r0 my $OP_COMPAREMEM = 4; # compare memory block -sub write_random_register_data($) +sub write_random_register_data($$) { - my ($fp_enabled) = @_; + my ($fp_enabled, $vsx_enabled) = @_; clear_vr_registers(); - write_random_ppc64_vrdata(); - if ($fp_enabled) { - # load floating point / SIMD registers - write_random_ppc64_fpdata(); + if ($vsx_enabled) { + write_random_ppc64_vsrdata(); + } else { + write_random_ppc64_vrdata(); + if ($fp_enabled) { + # load floating point / SIMD registers + write_random_ppc64_fpdata(); + } } write_random_regdata(); @@ -384,6 +411,7 @@ sub write_test_code($) my $condprob = $params->{ 'condprob' }; my $numinsns = $params->{ 'numinsns' }; my $fp_enabled = $params->{ 'fp_enabled' }; + my $vsx_enabled = $params->{ 'vsx_enabled' }; my $outfile = $params->{ 'outfile' }; my %insn_details = %{ $params->{ 'details' } }; @@ -410,7 +438,7 @@ sub write_test_code($) } # memblock setup doesn't clean its registers, so this must come afterwards. - write_random_register_data($fp_enabled); + write_random_register_data($fp_enabled, $vsx_enabled); for my $i (1..$numinsns) { my $insn_enc = $keys[int rand (@keys)]; @@ -421,7 +449,7 @@ sub write_test_code($) # Rewrite the registers periodically. This avoids the tendency # for the VFP registers to decay to NaNs and zeroes. if ($periodic_reg_random && ($i % 100) == 0) { - write_random_register_data($fp_enabled); + write_random_register_data($fp_enabled, $vsx_enabled); } progress_update($i); } From 689f2627894dfeadfe6f75bd66a5c577a3003dc1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Mon, 31 Oct 2022 10:44:14 -0300 Subject: [PATCH 08/22] ppc64: comment out insns removed in PowerISA v3.0b [ferst: LDMX; comment instead of removal] --- ppc64.risu | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/ppc64.risu b/ppc64.risu index a27e4fd..1a97814 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -917,10 +917,11 @@ LDBRX PPC64LE 011111 rt:5 ra:5 rb:5 10000101000 \ !constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \ !memory { reg_plus_reg($ra, $rb); } +# LDMX was removed in PowerISA v3.0b # format:X book:I page:54 v3.0 PI ldmx Load Dword Monitored Indexed -LDMX PPC64LE 011111 rt:5 ra:5 rb:5 01001101010 \ -!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \ -!memory { reg_plus_reg($ra, $rb); } +#LDMX PPC64LE 011111 rt:5 ra:5 rb:5 01001101010 \ +#!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \ +#!memory { reg_plus_reg($ra, $rb); } # format:DS book:I page:53 PPC ldu Load Dword with Update LDU PPC64LE 111010 rt:5 ra:5 imm:14 01 \ @@ -3156,10 +3157,11 @@ XVCMPGTSP PPC64LE 111100 t:5 a:5 b:5 01001011 ax:1 bx:1 tx:1 # format:XX3 book:I page:672 v2.06 xvcmpgtsp[.] VSX Vector Compare Greater Than SP XVCMPGTSPd PPC64LE 111100 t:5 a:5 b:5 11001011 ax:1 bx:1 tx:1 +# XVCMPNEDP[.] was removed in Power ISA v3.0b # format:XX3 book:I page:673 v3.0 xvcmpnedp[.] VSX Vector Compare Not Equal Double-Precision -XVCMPNEDP PPC64LE 111100 t:5 a:5 b:5 01111011 ax:1 bx:1 tx:1 +#XVCMPNEDP PPC64LE 111100 t:5 a:5 b:5 01111011 ax:1 bx:1 tx:1 # format:XX3 book:I page:673 v3.0 xvcmpnedp[.] VSX Vector Compare Not Equal Double-Precision -XVCMPNEDPd PPC64LE 111100 t:5 a:5 b:5 11111011 ax:1 bx:1 tx:1 +#XVCMPNEDPd PPC64LE 111100 t:5 a:5 b:5 11111011 ax:1 bx:1 tx:1 # format:XX3 book:I page:674 v3.0 xvcmpnesp[.] VSX Vector Compare Not Equal Single-Precision XVCMPNESP PPC64LE 111100 t:5 a:5 b:5 01011011 ax:1 bx:1 tx:1 From fc6b1016d87d1c014d4784b3421bfeb4629c5409 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Mon, 31 Oct 2022 09:27:29 -0300 Subject: [PATCH 09/22] ppc64: comment out insns that can't be tested with risu ADDPCIS uses the program counter, which depends on where the image was loaded. DARN is non-deterministic by definition, we can't compare the results between executions. --- ppc64.risu | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ppc64.risu b/ppc64.risu index 1a97814..0bd5719 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -87,8 +87,8 @@ ADDMEdo PPC64LE 011111 rt:5 ra:5 0000010111010101 \ !constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; } # format:DX book:I page:69 v3.0 addpcis Add PC Immediate Shifted -ADDPCIS PPC64LE 010011 rt:5 db:5 da:10 00010 dc:1 \ -!constraints { $rt != 1 && $rt != 13; } +#ADDPCIS PPC64LE 010011 rt:5 db:5 da:10 00010 dc:1 \ +#!constraints { $rt != 1 && $rt != 13; } # format:XO book:I page:73 v:P1 SR addze Add to Zero Extended ADDZE PPC64LE 011111 rt:5 ra:5 0000000110010100 \ @@ -276,8 +276,8 @@ DADDQ PPC64LE 111111 frtp:5 frap:5 frbp:5 00000000100 DADDQd PPC64LE 111111 frtp:5 frap:5 frbp:5 00000000101 # format:X book:I page:79 v3.0 darn Deliver A Random Number -DARN PPC64LE 011111 rt:5 000 l:2 0000010111100110 \ -!constraints { $rt != 1 && $rt != 13 && $l != 3; } +#DARN PPC64LE 011111 rt:5 000 l:2 0000010111100110 \ +#!constraints { $rt != 1 && $rt != 13 && $l != 3; } # format:X book:I page:217 v2.06 dcffix DFP Convert From Fixed DCFFIX PPC64LE 111011 frt:5 00000 frb:5 11001000100 From 6c13f474b4a95ea56b2f2c90d8d1c6ef0e16a2bd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?V=C3=ADctor=20Colombo?= Date: Mon, 31 Oct 2022 10:47:32 -0300 Subject: [PATCH 10/22] ppc64: Add fr*p constraints in ppc64.risu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some instructions use a pair of fp registers, represented by fr*p instead of just fr* (e.g. frap, frbp). These have the special property that they have to be an even-odd pair, starting at the even one. Otherwise, the instruction is malformed This patch adds constraints to these instructions to garantee the selected registers are even. Signed-off-by: Víctor Colombo --- ppc64.risu | 129 +++++++++++++++++++++++++++++++++++------------------ 1 file changed, 86 insertions(+), 43 deletions(-) diff --git a/ppc64.risu b/ppc64.risu index 0bd5719..cba66cd 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -271,9 +271,11 @@ DADD PPC64LE 111011 frt:5 fra:5 frb:5 00000000100 DADDd PPC64LE 111011 frt:5 fra:5 frb:5 00000000101 # format:X book:I page:195 v2.05 daddq DFP Add Quad -DADDQ PPC64LE 111111 frtp:5 frap:5 frbp:5 00000000100 +DADDQ PPC64LE 111111 frtp:5 frap:5 frbp:5 00000000100 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:195 v2.05 daddq. DFP Add Quad -DADDQd PPC64LE 111111 frtp:5 frap:5 frbp:5 00000000101 +DADDQd PPC64LE 111111 frtp:5 frap:5 frbp:5 00000000101 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:79 v3.0 darn Deliver A Random Number #DARN PPC64LE 011111 rt:5 000 l:2 0000010111100110 \ @@ -285,21 +287,25 @@ DCFFIX PPC64LE 111011 frt:5 00000 frb:5 11001000100 DCFFIXd PPC64LE 111011 frt:5 00000 frb:5 11001000101 # format:X book:I page:217 v2.05 dcffixq DFP Convert From Fixed Quad -DCFFIXQ PPC64LE 111111 frt:5 00000 frbp:5 11001000100 +DCFFIXQ PPC64LE 111111 frt:5 00000 frbp:5 11001000100 \ +!constraints { $frbp % 2 == 0; } # format:X book:I page:217 v2.05 dcffixq. DFP Convert From Fixed Quad -DCFFIXQd PPC64LE 111111 frt:5 00000 frbp:5 11001000101 +DCFFIXQd PPC64LE 111111 frt:5 00000 frbp:5 11001000101 \ +!constraints { $frbp % 2 == 0; } # format:X book:I page:201 v2.05 dcmpo DFP Compare Ordered DCMPO PPC64LE 111011 bf:3 00 fra:5 frb:5 00100000100 # format:X book:I page:201 v2.05 dcmpoq DFP Compare Ordered Quad -DCMPOQ PPC64LE 111111 bf:3 00 frap:5 frbp:5 00100000100 +DCMPOQ PPC64LE 111111 bf:3 00 frap:5 frbp:5 00100000100 \ +!constraints { $frap % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:200 v2.05 dcmpu DFP Compare Unordered DCMPU PPC64LE 111011 bf:3 00 fra:5 frb:5 10100000100 # format:X book:I page:200 v2.05 dcmpuq DFP Compare Unordered Quad -DCMPUQ PPC64LE 111111 bf:3 00 frap:5 frbp:5 10100000100 +DCMPUQ PPC64LE 111111 bf:3 00 frap:5 frbp:5 10100000100 \ +!constraints { $frap % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:215 v2.05 dctdp DFP Convert To DFP Long DCTDP PPC64LE 111011 frt:5 00000 frb:5 01000000100 @@ -312,14 +318,18 @@ DCTFIX PPC64LE 111011 frt:5 00000 frb:5 01001000100 DCTFIXd PPC64LE 111011 frt:5 00000 frb:5 01001000101 # format:X book:I page:217 v2.05 dctfixq DFP Convert To Fixed Quad -DCTFIXQ PPC64LE 111111 frt:5 00000 frbq:5 01001000100 +DCTFIXQ PPC64LE 111111 frt:5 00000 frbp:5 01001000100 \ +!constraints { $frbp % 2 == 0; } # format:X book:I page:217 v2.05 dctfixq. DFP Convert To Fixed Quad -DCTFIXQd PPC64LE 111111 frt:5 00000 frbq:5 01001000101 +DCTFIXQd PPC64LE 111111 frt:5 00000 frbp:5 01001000101 \ +!constraints { $frbp % 2 == 0; } # format:X book:I page:215 v2.05 dctqpq DFP Convert To DFP Extended -DCTQPQ PPC64LE 111111 frtp:5 00000 frb:5 01000000100 +DCTQPQ PPC64LE 111111 frtp:5 00000 frb:5 01000000100 \ +!constraints { $frtp % 2 == 0; } # format:X book:I page:215 v2.05 dctqpq. DFP Convert To DFP Extended -DCTQPQd PPC64LE 111111 frtp:5 00000 frb:5 01000000101 +DCTQPQd PPC64LE 111111 frtp:5 00000 frb:5 01000000101 \ +!constraints { $frtp % 2 == 0; } # format:X book:I page:219 v2.05 ddedpd DFP Decode DPD To BCD DDEDPD PPC64LE 111011 frt:5 sp:2 000 frb:5 01010000100 @@ -327,9 +337,11 @@ DDEDPD PPC64LE 111011 frt:5 sp:2 000 frb:5 01010000100 DDEDPDd PPC64LE 111011 frt:5 sp:2 000 frb:5 01010000101 # format:X book:I page:219 v2.05 ddedpdq DFP Decode DPD To BCD Quad -DDEDPDQ PPC64LE 111111 frtp:5 sp:2 000 frbp:5 01010000100 +DDEDPDQ PPC64LE 111111 frtp:5 sp:2 000 frbp:5 01010000100 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:219 v2.05 ddedpdq. DFP Decode DPD To BCD Quad -DDEDPDQd PPC64LE 111111 frtp:5 sp:2 000 frbp:5 01010000101 +DDEDPDQd PPC64LE 111111 frtp:5 sp:2 000 frbp:5 01010000101 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:198 v2.05 ddiv DFP Divide DDIV PPC64LE 111011 frt:5 fra:5 frb:5 10001000100 @@ -337,9 +349,11 @@ DDIV PPC64LE 111011 frt:5 fra:5 frb:5 10001000100 DDIVd PPC64LE 111011 frt:5 fra:5 frb:5 10001000101 # format:X book:I page:198 v2.05 ddivq DFP Divide Quad -DDIVQ PPC64LE 111111 frtp:5 frap:5 frbp:5 10001000100 +DDIVQ PPC64LE 111111 frtp:5 frap:5 frbp:5 10001000100 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:198 v2.05 ddivq. DFP Divide Quad -DDIVQd PPC64LE 111111 frtp:5 frap:5 frbp:5 10001000101 +DDIVQd PPC64LE 111111 frtp:5 frap:5 frbp:5 10001000101 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:219 v2.05 denbcd DFP Encode BCD To DPD DENBCD PPC64LE 111011 frt:5 s:1 0000 frb:5 11010000100 @@ -347,9 +361,11 @@ DENBCD PPC64LE 111011 frt:5 s:1 0000 frb:5 11010000100 DENBCDd PPC64LE 111011 frt:5 s:1 0000 frb:5 11010000101 # format:X book:I page:219 v2.05 denbcdq DFP Encode BCD To DPD Quad -DENBCDQ PPC64LE 111111 frtp:5 s:1 0000 frbp:5 11010000100 +DENBCDQ PPC64LE 111111 frtp:5 s:1 0000 frbp:5 11010000100 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:219 v2.05 denbcdq. DFP Encode BCD To DPD Quad -DENBCDQd PPC64LE 111111 frtp:5 s:1 0000 frbp:5 11010000101 +DENBCDQd PPC64LE 111111 frtp:5 s:1 0000 frbp:5 11010000101 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:220 v2.05 diex DFP Insert Exponent DIEX PPC64LE 111011 frt:5 fra:5 frb:5 11011000100 @@ -357,9 +373,11 @@ DIEX PPC64LE 111011 frt:5 fra:5 frb:5 11011000100 DIEXd PPC64LE 111011 frt:5 fra:5 frb:5 11011000101 # format:X book:I page:220 v2.05 diexq DFP Insert Exponent Quad -DIEXQ PPC64LE 111111 frtp:5 fra:5 frbp:5 11011000100 +DIEXQ PPC64LE 111111 frtp:5 fra:5 frbp:5 11011000100 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:220 v2.05 diexq. DFP Insert Exponent Quad -DIEXQd PPC64LE 111111 frtp:5 fra:5 frbp:5 11011000101 +DIEXQd PPC64LE 111111 frtp:5 fra:5 frbp:5 11011000101 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:XO book:I page:82 PPC SR divd Divide Dword DIVD PPC64LE 011111 rt:5 ra:5 rb:5 01111010010 \ @@ -486,19 +504,25 @@ DQUAI PPC64LE 111011 frt:5 te:5 frb:5 rmc:2 010000110 DQUAId PPC64LE 111011 frt:5 te:5 frb:5 rmc:2 010000111 # format:Z23 book:I page:205 v2.05 dquaiq DFP Quantize Immediate Quad -DQUAIQ PPC64LE 111111 frtp:5 te:5 frbp:5 rmc:2 010000110 +DQUAIQ PPC64LE 111111 frtp:5 te:5 frbp:5 rmc:2 010000110 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:Z23 book:I page:205 v2.05 dquaiq. DFP Quantize Immediate Quad -DQUAIQd PPC64LE 111111 frtp:5 te:5 frbp:5 rmc:2 010000111 +DQUAIQd PPC64LE 111111 frtp:5 te:5 frbp:5 rmc:2 010000111 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:Z23 book:I page:206 v2.05 dquaq DFP Quantize Quad -DQUAQ PPC64LE 111111 frtp:5 frap:5 frbp:5 rmc:2 000000110 +DQUAQ PPC64LE 111111 frtp:5 frap:5 frbp:5 rmc:2 000000110 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0 && $frbp % 2 == 0; } # format:Z23 book:I page:206 v2.05 dquaq. DFP Quantize Quad -DQUAQd PPC64LE 111111 frtp:5 frap:5 frbp:5 rmc:2 000000111 +DQUAQd PPC64LE 111111 frtp:5 frap:5 frbp:5 rmc:2 000000111 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:216 v2.05 drdpq DFP Round To DFP Long -DRDPQ PPC64LE 111111 frtp:5 00000 frbp:5 11000000100 +DRDPQ PPC64LE 111111 frtp:5 00000 frbp:5 11000000100 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:216 v2.05 drdpq. DFP Round To DFP Long -DRDPQd PPC64LE 111111 frtp:5 00000 frbp:5 11000000101 +DRDPQd PPC64LE 111111 frtp:5 00000 frbp:5 11000000101 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:Z23 book:I page:213 v2.05 drintn DFP Round To FP Integer Without Inexact DRINTN PPC64LE 111011 frt:5 0000 r:1 frb:5 rmc:2 111000110 @@ -506,9 +530,11 @@ DRINTN PPC64LE 111011 frt:5 0000 r:1 frb:5 rmc:2 111000110 DRINTNd PPC64LE 111011 frt:5 0000 r:1 frb:5 rmc:2 111000111 # format:Z23 book:I page:213 v2.05 drintnq DFP Round To FP Integer Without Inexact Quad -DRINTNQ PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 111000110 +DRINTNQ PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 111000110 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:Z23 book:I page:213 v2.05 drintnq. DFP Round To FP Integer Without Inexact Quad -DRINTNQd PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 111000111 +DRINTNQd PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 111000111 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:Z23 book:I page:211 v2.05 drintx DFP Round To FP Integer With Inexact DRINTX PPC64LE 111011 frt:5 0000 r:1 frb:5 rmc:2 011000110 @@ -516,9 +542,11 @@ DRINTX PPC64LE 111011 frt:5 0000 r:1 frb:5 rmc:2 011000110 DRINTXd PPC64LE 111011 frt:5 0000 r:1 frb:5 rmc:2 011000111 # format:Z23 book:I page:211 v2.05 drintxq DFP Round To FP Integer With Inexact Quad -DRINTXQ PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 011000110 +DRINTXQ PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 011000110 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:Z23 book:I page:211 v2.05 drintxq. DFP Round To FP Integer With Inexact Quad -DRINTXQd PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 011000111 +DRINTXQd PPC64LE 111111 frtp:5 0000 r:1 frbp:5 rmc:2 011000111 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:Z23 book:I page:208 v2.05 drrnd DFP Reround DRRND PPC64LE 111011 frt:5 fra:5 frb:5 rmc:2 001000110 @@ -526,9 +554,11 @@ DRRND PPC64LE 111011 frt:5 fra:5 frb:5 rmc:2 001000110 DRRNDd PPC64LE 111011 frt:5 fra:5 frb:5 rmc:2 001000111 # format:Z23 book:I page:208 v2.05 drrndq DFP Reround Quad -DRRNDQ PPC64LE 111111 frtp:5 fra:5 frbp:5 rmc:2 001000110 +DRRNDQ PPC64LE 111111 frtp:5 fra:5 frbp:5 rmc:2 001000110 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:Z23 book:I page:208 v2.05 drrndq. DFP Reround Quad -DRRNDQd PPC64LE 111111 frtp:5 fra:5 frbp:5 rmc:2 001000111 +DRRNDQd PPC64LE 111111 frtp:5 fra:5 frbp:5 rmc:2 001000111 \ +!constraints { $frtp % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:216 v2.05 drsp DFP Round To DFP Short DRSP PPC64LE 111011 frt:5 00000 frb:5 11000000100 @@ -541,9 +571,11 @@ DSCLI PPC64LE 111011 frt:5 fra:5 sh:6 0010000100 DSCLId PPC64LE 111011 frt:5 fra:5 sh:6 0010000101 # format:Z22 book:I page:222 v2.05 dscliq DFP Shift Significand Left Immediate Quad -DSCLIQ PPC64LE 111111 frtp:5 frap:5 sh:6 0010000100 +DSCLIQ PPC64LE 111111 frtp:5 frap:5 sh:6 0010000100 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0; } # format:Z22 book:I page:222 v2.05 dscliq. DFP Shift Significand Left Immediate Quad -DSCLIQd PPC64LE 111111 frtp:5 frap:5 sh:6 0010000101 +DSCLIQd PPC64LE 111111 frtp:5 frap:5 sh:6 0010000101 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0; } # format:Z22 book:I page:222 v2.05 dscri DFP Shift Significand Right Immediate DSCRI PPC64LE 111011 frt:5 fra:5 sh:6 0011000100 @@ -551,9 +583,11 @@ DSCRI PPC64LE 111011 frt:5 fra:5 sh:6 0011000100 DSCRId PPC64LE 111011 frt:5 fra:5 sh:6 0011000101 # format:Z22 book:I page:222 v2.05 dscriq DFP Shift Significand Right Immediate Quad -DSCRIQ PPC64LE 111111 frtp:5 frap:5 sh:6 0011000100 +DSCRIQ PPC64LE 111111 frtp:5 frap:5 sh:6 0011000100 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0; } # format:Z22 book:I page:222 v2.05 dscriq. DFP Shift Significand Right Immediate Quad -DSCRIQd PPC64LE 111111 frtp:5 frap:5 sh:6 0011000101 +DSCRIQd PPC64LE 111111 frtp:5 frap:5 sh:6 0011000101 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0; } # format:X book:I page:195 v2.05 dsub DFP Subtract DSUB PPC64LE 111011 frt:5 fra:5 frb:5 10000000100 @@ -561,27 +595,33 @@ DSUB PPC64LE 111011 frt:5 fra:5 frb:5 10000000100 DSUBd PPC64LE 111011 frt:5 fra:5 frb:5 10000000101 # format:X book:I page:195 v2.05 dsubq DFP Subtract Quad -DSUBQ PPC64LE 111111 frtp:5 frap:5 frbp:5 10000000100 +DSUBQ PPC64LE 111111 frtp:5 frap:5 frbp:5 10000000100 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:195 v2.05 dsubq. DFP Subtract Quad -DSUBQd PPC64LE 111111 frtp:5 frap:5 frbp:5 10000000101 +DSUBQd PPC64LE 111111 frtp:5 frap:5 frbp:5 10000000101 \ +!constraints { $frtp % 2 == 0 && $frap % 2 == 0 && $frbp % 2 == 0; } # format:Z22 book:I page:202 v2.05 dtstdc DFP Test Data Class DTSTDC PPC64LE 111011 bf:3 00 fra:5 dcm:6 0110000100 # format:Z22 book:I page:202 v2.05 dtstdcq DFP Test Data Class Quad -DTSTDCQ PPC64LE 111111 bf:3 00 frap:5 dcm:6 0110000100 +DTSTDCQ PPC64LE 111111 bf:3 00 frap:5 dcm:6 0110000100 \ +!constraints { $frap % 2 == 0; } # format:Z22 book:I page:202 v2.05 dtstdg DFP Test Data Group -DTSTDG PPC64LE 111011 bf:3 00 frap:5 dgm:6 0111000100 +DTSTDG PPC64LE 111011 bf:3 00 frap:5 dgm:6 0111000100 \ +!constraints { $frap % 2 == 0; } # format:Z22 book:I page:202 v2.05 dtstdgq DFP Test Data Group Quad -DTSTDGQ PPC64LE 111111 bf:3 00 frap:5 dgm:6 0111000100 +DTSTDGQ PPC64LE 111111 bf:3 00 frap:5 dgm:6 0111000100 \ +!constraints { $frap % 2 == 0; } # format:X book:I page:203 v2.05 dtstex DFP Test Exponent DTSTEX PPC64LE 111011 bf:3 00 fra:5 frb:5 00101000100 # format:X book:I page:203 v2.05 dtstexq DFP Test Exponent Quad -DTSTEXQ PPC64LE 111111 bf:3 00 frap:5 frbp:5 00101000100 +DTSTEXQ PPC64LE 111111 bf:3 00 frap:5 frbp:5 00101000100 \ +!constraints { $frap % 2 == 0 && $frbp % 2 == 0; } # format:X book:I page:204 v2.05 dtstsf DFP Test Significance DTSTSF PPC64LE 111011 bf:3 0 fra:6 frb:5 10101000100 @@ -590,7 +630,8 @@ DTSTSF PPC64LE 111011 bf:3 0 fra:6 frb:5 10101000100 DTSTSFI PPC64LE 111011 bf:3 0 uim:6 frb:5 10101000110 # format:X book:I page:204 v3.0 dtstsfiq DFP Test Significance Immediate Quad -DTSTSFIQ PPC64LE 111111 bf:3 0 uim:6 frbp:5 10101000110 +DTSTSFIQ PPC64LE 111111 bf:3 0 uim:6 frbp:5 10101000110 \ +!constraints { $frbp % 2 == 0; } # format:X book:I page:204 v2.05 dtstsfq DFP Test Significance Quad DTSTSFQ PPC64LE 111111 bf:3 0 fra:6 frb:5 10101000100 @@ -601,9 +642,11 @@ DXEX PPC64LE 111011 frt:5 00000 frb:5 01011000100 DXEXd PPC64LE 111011 frt:5 00000 frb:5 01011000101 # format:X book:I page:220 v2.05 dxexq DFP Extract Exponent Quad -DEXEQ PPC64LE 111111 frt:5 00000 frbp:5 01011000100 +DXEXQ PPC64LE 111111 frt:5 00000 frbp:5 01011000100 \ +!constraints { $frbp % 2 == 0; } # format:X book:I page:220 v2.05 dxexq. DFP Extract Exponent Quad -DEXEQd PPC64LE 111111 frt:5 00000 frbp:5 01011000101 +DXEXQd PPC64LE 111111 frt:5 00000 frbp:5 01011000101 \ +!constraints { $frbp % 2 == 0; } # format:X book:I page:94 v:P1 SR eqv Equivalent EQV PPC64LE 011111 rs:5 ra:5 rb:5 01000111000 \ From dc26f26371750f4b0684a033bba77b53aeb156e1 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Mon, 24 Oct 2022 15:12:40 -0300 Subject: [PATCH 11/22] ppc64: fix addg6s opcode --- ppc64.risu | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ppc64.risu b/ppc64.risu index cba66cd..179b796 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -54,7 +54,7 @@ ADDEdo PPC64LE 011111 rt:5 ra:5 rb:5 10100010101 \ !constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; } # format:XO book:I page:110 v:2.06 addg6s Add & Generate Sixes -ADDG6S PPC64LE 111111 rt:5 ra:5 rb:5 00010010100 \ +ADDG6S PPC64LE 011111 rt:5 ra:5 rb:5 0 001001010 0 \ !constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; } # format:D book:I page:68 v:P1 addi Add Immediate From af766877e6a6318e93520eead93db3c641b00d07 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Mon, 24 Oct 2022 15:33:17 -0300 Subject: [PATCH 12/22] ppc64: add !memory block to load/store insns Also adds "$ra != $rb" and "$ra != 0" constraints to avoid the current limitations of reg_plus_reg and reg_plus_imm implementations. --- ppc64.risu | 54 ++++++++++++++++++++++++++++++++++++------------------ 1 file changed, 36 insertions(+), 18 deletions(-) diff --git a/ppc64.risu b/ppc64.risu index 179b796..ed8e196 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -1197,11 +1197,13 @@ LXSDX PPC64LE 011111 t:5 ra:5 rb:5 1001001100 tx:1 \ # format:XX1 book:I page:483 v3.0 lxsibzx Load VSX Scalar as Integer Byte & Zero Indexed LXSIBZX PPC64LE 011111 t:5 ra:5 rb:5 1100001101 tx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:483 v3.0 lxsihzx Load VSX Scalar as Integer Hword & Zero Indexed LXSIHZX PPC64LE 011111 t:5 ra:5 rb:5 1100101101 tx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:484 v2.07 lxsiwax Load VSX Scalar as Integer Word Algebraic Indexed LXSIWAX PPC64LE 011111 t:5 ra:5 rb:5 0001001100 tx:1 \ @@ -1215,7 +1217,8 @@ LXSIWZX PPC64LE 011111 t:5 ra:5 rb:5 0000001100 tx:1 \ # format:DS book:I page:486 v3.0 lxssp Load VSX Scalar Single LXSSP PPC64LE 111001 vrt:5 ra:5 imm:14 11 \ -!constraints { $ra != 1 && $ra != 13; } +!constraints { $ra != 1 && $ra != 13 && $ra != 0; } \ +!memory { reg_plus_imm($ra, $imm << 2); } # format:XX1 book:I page:486 v2.07 lxsspx Load VSX Scalar SP Indexed LXSSPX PPC64LE 011111 t:5 ra:5 rb:5 1000001100 tx:1 \ @@ -1224,11 +1227,13 @@ LXSSPX PPC64LE 011111 t:5 ra:5 rb:5 1000001100 tx:1 \ # format:DQ book:I page:493 v3.0 lxv Load VSX Vector LXV PPC64LE 111101 t:5 ra:5 imm:12 001 tx:1 \ -!constraints { $ra != 1 && $ra != 13; } +!constraints { $ra != 1 && $ra != 13 && $ra != 0; } \ +!memory { reg_plus_imm($ra, $imm); } # format:XX1 book:I page:488 v3.0 lxvb16x Load VSX Vector Byte*16 Indexed LXVB16X PPC64LE 011111 t:5 ra:5 rb:5 1101101100 tx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:489 v2.06 lxvd2x Load VSX Vector Dword*2 Indexed LXVD2X PPC64LE 011111 t:5 ra:5 rb:5 1101001100 tx:1 \ @@ -1242,15 +1247,18 @@ LXVDSX PPC64LE 011111 t:5 ra:5 rb:5 0101001100 tx:1 \ # format:XX1 book:I page:496 v3.0 lxvh8x Load VSX Vector Hword*8 Indexed LXVH8X PPC64LE 011111 t:5 ra:5 rb:5 1100101100 tx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:490 v3.0 lxvl Load VSX Vector with Length LXVL PPC64LE 011111 t:5 ra:5 rb:5 0100001101 tx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:492 v3.0 lxvll Load VSX Vector Left-justified with Length LXVLL PPC64LE 011111 t:5 ra:5 rb:5 0100101101 tx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:497 v2.06 lxvw4x Load VSX Vector Word*4 Indexed LXVW4X PPC64LE 011111 t:5 ra:5 rb:5 1100001100 tx:1 \ @@ -1259,11 +1267,13 @@ LXVW4X PPC64LE 011111 t:5 ra:5 rb:5 1100001100 tx:1 \ # format:XX1 book:I page:498 v3.0 lxvwsx Load VSX Vector Word & Splat Indexed LXVWSX PPC64LE 011111 t:5 ra:5 rb:5 0101101100 tx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:493 v3.0 lxvx Load VSX Vector Indexed LXVX PPC64LE 011111 t:5 ra:5 rb:5 0100001100 tx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:VA book:I page:81 v3.0 maddhd Multiply-Add High Dword MADDHD PPC64LE 000100 rt:5 ra:5 rb:5 rc:5 110000 \ @@ -1850,11 +1860,13 @@ STXSDX PPC64LE 011111 s:5 ra:5 rb:5 1011001100 sx:1 \ # format:XX1 book:I page:500 v3.0 stxsibx Store VSX Scalar as Integer Byte Indexed STXSIBX PPC64LE 011111 s:5 ra:5 rb:5 11100 01101 sx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:500 v3.0 stxsihx Store VSX Scalar as Integer Hword Indexed STXSIHX PPC64LE 011111 s:5 ra:5 rb:5 11101 01101 sx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:501 v2.07 stxsiwx Store VSX Scalar as Integer Word Indexed STXSIWX PPC64LE 011111 s:5 ra:5 rb:5 00100 01100 sx:1 \ @@ -1873,11 +1885,13 @@ STXSSPX PPC64LE 011111 s:5 ra:5 rb:5 10100 01100 sx:1 \ # format:DQ book:I page:508 v3.0 stxv Store VSX Vector STXV PPC64LE 111101 s:5 ra:5 imm:12 dx:1 101 \ -!constraints { $ra != 1 && $ra != 13; } +!constraints { $ra != 1 && $ra != 13 && $ra != 0; } \ +!memory { reg_plus_imm($ra, $imm << 4); } # format:XX1 book:I page:504 v3.0 stxvb16x Store VSX Vector Byte*16 Indexed STXVB16X PPC64LE 011111 s:5 ra:5 rb:5 11111 01100 sx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:505 v2.06 stxvd2x Store VSX Vector Dword*2 Indexed STXVD2X PPC64LE 011111 s:5 ra:5 rb:5 11110 01100 sx:1 \ @@ -1886,15 +1900,18 @@ STXVD2X PPC64LE 011111 s:5 ra:5 rb:5 11110 01100 sx:1 \ # format:XX1 book:I page:506 v3.0 stxvh8x Store VSX Vector Hword*8 Indexed STXVH8X PPC64LE 011111 s:5 ra:5 rb:5 11101 01100 sx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:508 v3.0 stxvl Store VSX Vector with Length STXVL PPC64LE 011111 s:5 ra:5 rb:5 01100 01101 sx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:510 v3.0 stxvll Store VSX Vector Left-justified with Length STXVLL PPC64LE 011111 s:5 ra:5 rb:5 01101 01101 sx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XX1 book:I page:507 v2.06 stxvw4x Store VSX Vector Word*4 Indexed STXVW4X PPC64LE 011111 s:5 ra:5 rb:5 11100 01100 sx:1 \ @@ -1903,7 +1920,8 @@ STXVW4X PPC64LE 011111 s:5 ra:5 rb:5 11100 01100 sx:1 \ # format:XX1 book:I page:511 v3.0 stxvx Store VSX Vector Indexed STXVX PPC64LE 011111 s:5 ra:5 rb:5 01100 01100 sx:1 \ -!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } # format:XO book:I page:70 PPC SR subf[o][.] Subtract From SUBF PPC64LE 011111 rt:5 ra:5 rb:5 00001010000 \ From dfa8f4d142c62a45134321ab887e7a9365e109b8 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Thu, 27 Oct 2022 15:39:42 -0300 Subject: [PATCH 13/22] ppc64: Fix LXV opcode and !memory Unlike the other VSX instructions, the TX field of LVX is not the last bit. Also, the immediate is multiplied by 16 to calculate EA. --- ppc64.risu | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ppc64.risu b/ppc64.risu index ed8e196..594df99 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -1226,9 +1226,9 @@ LXSSPX PPC64LE 011111 t:5 ra:5 rb:5 1000001100 tx:1 \ !memory { reg_plus_reg($ra, $rb); } # format:DQ book:I page:493 v3.0 lxv Load VSX Vector -LXV PPC64LE 111101 t:5 ra:5 imm:12 001 tx:1 \ +LXV PPC64LE 111101 t:5 ra:5 imm:12 tx:1 001 \ !constraints { $ra != 1 && $ra != 13 && $ra != 0; } \ -!memory { reg_plus_imm($ra, $imm); } +!memory { reg_plus_imm($ra, $imm << 4); } # format:XX1 book:I page:488 v3.0 lxvb16x Load VSX Vector Byte*16 Indexed LXVB16X PPC64LE 011111 t:5 ra:5 rb:5 1101101100 tx:1 \ From c4eab46c7567bcfcfccc99fedd0292366c157ee2 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Thu, 27 Oct 2022 15:45:40 -0300 Subject: [PATCH 14/22] ppc64: Fix LXVL[L]/STXVL[L] memory block EA is not calculated with "reg plus reg" for these instructions. Instead, RA is the base register to access up to 16 bytes, according to RB[0:7] value. Also, abuse the memory block to put a valid value in RB. -- Power ISA says that the results are "boundedly undefined" if the contents of bits 8:63 of RB are not equal to zero. I'd expect the hardware to ignore those bits, but we observed SIGSEGVs on hardware if we use just reg($ra) and let any random value in RB. --- ppc64.risu | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/ppc64.risu b/ppc64.risu index 594df99..8b9a341 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -1253,12 +1253,12 @@ LXVH8X PPC64LE 011111 t:5 ra:5 rb:5 1100101100 tx:1 \ # format:XX1 book:I page:490 v3.0 lxvl Load VSX Vector with Length LXVL PPC64LE 011111 t:5 ra:5 rb:5 0100001101 tx:1 \ !constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ -!memory { reg_plus_reg($ra, $rb); } +!memory { write_mov_ri($rb, rand(0xff)); reg($ra); } # format:XX1 book:I page:492 v3.0 lxvll Load VSX Vector Left-justified with Length LXVLL PPC64LE 011111 t:5 ra:5 rb:5 0100101101 tx:1 \ !constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ -!memory { reg_plus_reg($ra, $rb); } +!memory { write_mov_ri($rb, rand(0xff)); reg($ra); } # format:XX1 book:I page:497 v2.06 lxvw4x Load VSX Vector Word*4 Indexed LXVW4X PPC64LE 011111 t:5 ra:5 rb:5 1100001100 tx:1 \ @@ -1906,12 +1906,12 @@ STXVH8X PPC64LE 011111 s:5 ra:5 rb:5 11101 01100 sx:1 \ # format:XX1 book:I page:508 v3.0 stxvl Store VSX Vector with Length STXVL PPC64LE 011111 s:5 ra:5 rb:5 01100 01101 sx:1 \ !constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ -!memory { reg_plus_reg($ra, $rb); } +!memory { write_mov_ri($rb, rand(0xff)); reg($ra); } # format:XX1 book:I page:510 v3.0 stxvll Store VSX Vector Left-justified with Length STXVLL PPC64LE 011111 s:5 ra:5 rb:5 01101 01101 sx:1 \ !constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ -!memory { reg_plus_reg($ra, $rb); } +!memory { write_mov_ri($rb, rand(0xff)); reg($ra); } # format:XX1 book:I page:507 v2.06 stxvw4x Store VSX Vector Word*4 Indexed STXVW4X PPC64LE 011111 s:5 ra:5 rb:5 11100 01100 sx:1 \ From c90ca02f2ed58c749ad594383c475c4f216d69a0 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Thu, 27 Oct 2022 16:00:38 -0300 Subject: [PATCH 15/22] ppc64: fix STQ constraint If $ra is used as one of the source registers, we'll store a value that depends on the stack pointer in the memory block. If a load instruction later reads this value, the register comparison will fail mysteriously. --- ppc64.risu | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ppc64.risu b/ppc64.risu index 8b9a341..5545d65 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -1790,7 +1790,7 @@ STSWI PPC64BE 011111 rs:5 ra:5 rb:5 10110101010 \ # format:DS book:I page:60 v2.03 stq Store Qword STQ PPC64BE 111110 rsp:5 ra:5 imm:14 10 \ -!constraints { $rsp % 2 == 0 && $ra != 1 && $ra != 13 && $ra != 0 && $rsp != $ra && $imm <= 8176; } \ +!constraints { $rsp % 2 == 0 && $rsp != 0 && $rsp != 12 && $ra != 1 && $ra != 13 && $ra != 0 && $rsp != ($ra & ~1) && $imm <= 8176; } \ !memory { reg_plus_imm($ra, $imm << 2); } # format:X book:I page:66 v:P1 stswx Store String Word Indexed From fa91ccf4a6a0eeaa5242c722f62813b50ec96e79 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Thu, 27 Oct 2022 16:19:32 -0300 Subject: [PATCH 16/22] ppc64: improve write_memblock_setup Currently, write_memblock_setup initializes 10000 bytes below the stack pointer with zeros. However, reg_plus_reg and reg_plus_imm make the instruction point to $r1+32 and $r1, respectively, causing access outside the stack frame. Change write_memblock_setup to initialize the memblock with random data, and use STDU to make $r1 point to the beginning of the block at the end. --- risugen_ppc64.pm | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index 10b18f8..5fcb55c 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -245,12 +245,11 @@ sub write_random_register_data($$) sub write_memblock_setup() { - # li r2, 0 - write_mov_ri(2, 0); - for (my $i = 0; $i < 10000; $i = $i + 8) { - # std r2, 0(r1) - my $imm = -$i; - insn32((0x3e << 26) | (2 << 21) | (1 << 16) | ($imm & 0xffff)); + for (my $i = 0; $i < 1024; $i = $i + 1) { + # li r2, $rand + write_mov_ri(2, rand(0xffffffff)); + # stdu r2, -8(r1) + insn32((0x3e << 26) | (2 << 21) | (1 << 16) | (-8 & 0xffff) | 1); } } From 962611c1f7231c6f4a9e7cbdbd947bf81e99dab6 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Mon, 31 Oct 2022 13:46:18 -0300 Subject: [PATCH 17/22] ppc64: some POWER10 insns patterns --- ppc64.risu | 186 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 186 insertions(+) diff --git a/ppc64.risu b/ppc64.risu index 5545d65..e8a2f48 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -220,6 +220,10 @@ CNTLZD PPC64LE 011111 rs:5 ra:5 0000000001110100 \ CNTLZDd PPC64LE 011111 rs:5 ra:5 0000000001110101 \ !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } +# format:X book:I page:105 v3.1 cntlzdm Count Leading Zeros Doubleword under bit Mask +CNTLZDM PPC64LE 011111 rs:5 ra:5 rb:5 0000111011 0 \ +!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13;} + # format:X book:I page:95 v:P1 SR cntlzw Count Leading Zeros Word CNTLZW PPC64LE 011111 rs:5 ra:5 0000000000110100 \ !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } @@ -234,6 +238,10 @@ CNTTZD PPC64LE 011111 rs:5 ra:5 0000010001110100 \ CNTTZDd PPC64LE 011111 rs:5 ra:5 0000010001110101 \ !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } +# format:X book:I page:105 v3.1 cnttzdm Count Trailing Zeros Doubleword under bit Mask +CNTTZDM PPC64LE 011111 rs:5 ra:5 rb:5 1000111011 0 \ +!constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13;} + # format:X book:I page:95 v3.0 cnttzw Count Trailing Zeros Word CNTTZW PPC64LE 011111 rs:5 ra:5 0000010000110100 \ !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } @@ -1260,6 +1268,26 @@ LXVLL PPC64LE 011111 t:5 ra:5 rb:5 0100101101 tx:1 \ !constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ !memory { write_mov_ri($rb, rand(0xff)); reg($ra); } +# format:X book:I page:635 v3.1 lxvrbx Load VSX Vector Rightmost Byte Indexed +LXVRBX PPC64LE 011111 t:5 ra:5 rb:5 0000001101 tx:1 \ +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } + +# format:X book:I page:636 v3.1 lxvrdx Load VSX Vector Rightmost Doubleword Indexed +LXVRDX PPC64LE 011111 t:5 ra:5 rb:5 0001101101 tx:1 \ +!constraints { $ra != $rb && $ra != 0 && $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } \ +!memory { reg_plus_reg($ra, $rb); } + +# format:X book:I page:637 v3.1 lxvrhx Load VSX Vector Rightmost Halfword Indexed +LXVRHX PPC64LE 011111 t:5 ra:5 rb:5 0000101101 tx:1 \ +!constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } + +# format:X book:I page:638 v3.1 lxvrwx Load VSX Vector Rightmost Word Indexed +LXVRWX PPC64LE 011111 t:5 ra:5 rb:5 0001001101 tx:1 \ +!constraints { $ra != $rb && $ra != 0 && $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } \ +!memory { reg_plus_reg($ra, $rb); } + # format:XX1 book:I page:497 v2.06 lxvw4x Load VSX Vector Word*4 Indexed LXVW4X PPC64LE 011111 t:5 ra:5 rb:5 1100001100 tx:1 \ !constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ @@ -1913,6 +1941,26 @@ STXVLL PPC64LE 011111 s:5 ra:5 rb:5 01101 01101 sx:1 \ !constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ !memory { write_mov_ri($rb, rand(0xff)); reg($ra); } +# format:X book:I page:659 v3.1 stxvrbx Store VSX Vector Rightmost Byte Indexed +STXVRBX PPC64LE 011111 s:5 ra:5 rb:5 0010001101 sx:1 \ +!constraints { $ra != 0 && $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ +!memory { reg_plus_reg($ra, $rb); } + +# format:X book:I page:659 v3.1 stxvrdx Store VSX Vector Rightmost Doubleword Indexed +STXVRDX PPC64LE 011111 s:5 ra:5 rb:5 0011101101 sx:1 \ +!constraints { $ra != 0 && $ra != $rb && $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } \ +!memory { reg_plus_reg($ra, $rb); } + +# format:X book:I page:660 v3.1 stxvrhx Store VSX Vector Rightmost Halfword Indexed +STXVRHX PPC64LE 011111 s:5 ra:5 rb:5 0010101101 sx:1 \ +!constraints { $ra != $rb && $ra != 0 && $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } \ +!memory { reg_plus_reg($ra, $rb); } + +# format:X book:I page:660 v3.1 stxvrwx Store VSX Vector Rightmost Word Indexed +STXVRWX PPC64LE 011111 s:5 ra:5 rb:5 0011001101 sx:1 \ +!constraints { $ra != $rb && $ra != 0 && $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13; } \ +!memory { reg_plus_reg($ra, $rb); } + # format:XX1 book:I page:507 v2.06 stxvw4x Store VSX Vector Word*4 Indexed STXVW4X PPC64LE 011111 s:5 ra:5 rb:5 11100 01100 sx:1 \ !constraints { $ra != 1 && $rb != 1 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rb; } \ @@ -2109,6 +2157,14 @@ VCIPHER PPC64LE 000100 vrt:5 vra:5 vrb:5 10100001000 # format:VX book:I page:336 v2.07 vcipherlast Vector AES Cipher Last VCIPHERLAST PPC64LE 000100 vrt:5 vra:5 vrb:5 10100001001 +# format:VX book:I page:481 v3.1 vclrlb Vector Clear Leftmost Bytes +VCLRLB PPC64LE 000100 vrt:5 vra:5 rb:5 00110001101 \ +!constraints { $rb != 1 && $rb != 13; } + +# format:VX book:I page:481 v3.1 vclrrb Vector Clear Rightmost Bytes +VCLRRB PPC64LE 000100 vrt:5 vra:5 rb:5 00111001101 \ +!constraints { $rb != 1 && $rb != 13; } + # format:VX book:I page:343 v2.07 vclzb Vector Count Leading Zeros Byte VCLZB PPC64LE 000100 vrt:5 00000 vrb:5 11100000010 @@ -2150,6 +2206,11 @@ VCMPEQUH PPC64LE 000100 vrt:5 vra:5 vrb:5 00001000110 # format:VC book:I page:306 v2.03 vcmpequh[.] Vector Compare Equal Unsigned Hword VCMPEQUHd PPC64LE 000100 vrt:5 vra:5 vrb:5 10001000110 +# format:VC book:I page:392 v3.1 vcmpequq[.] Vector Compare Equal Unsigned Word +VCMPEQUQ PPC64LE 000100 vrt:5 vra:5 vrb:5 00111000111 +# format:VC book:I page:392 v3.1 vcmpequq[.] Vector Compare Equal Unsigned Word +VCMPEQUQd PPC64LE 000100 vrt:5 vra:5 vrb:5 10111000111 + # format:VC book:I page:307 v2.03 vcmpequw[.] Vector Compare Equal Unsigned Word VCMPEQUW PPC64LE 000100 vrt:5 vra:5 vrb:5 00010000110 # format:VC book:I page:307 v2.03 vcmpequw[.] Vector Compare Equal Unsigned Word @@ -2180,6 +2241,11 @@ VCMPGTSH PPC64LE 000100 vrt:5 vra:5 vrb:5 01101000110 # format:VC book:I page:309 v2.03 vcmpgtsh[.] Vector Compare Greater Than Signed Hword VCMPGTSHd PPC64LE 000100 vrt:5 vra:5 vrb:5 11101000110 +# format:VC book:I page:397 v3.1 vcmpgtsq[.] Vector Compare Greater Than Signed Qword +VCMPGTSQ PPC64LE 000100 vrt:5 vra:5 vrb:5 01110000111 +# format:VC book:I page:397 v3.1 vcmpgtsq[.] Vector Compare Greater Than Signed Qword +VCMPGTSQd PPC64LE 000100 vrt:5 vra:5 vrb:5 11110000111 + # format:VC book:I page:309 v2.03 vcmpgtsw[.] Vector Compare Greater Than Signed Word VCMPGTSW PPC64LE 000100 vrt:5 vra:5 vrb:5 01110000110 # format:VC book:I page:309 v2.03 vcmpgtsw[.] Vector Compare Greater Than Signed Word @@ -2200,6 +2266,11 @@ VCMPGTUH PPC64LE 000100 vrt:5 vra:5 vrb:5 01001000110 # format:VC book:I page:311 v2.03 vcmpgtuh[.] Vector Compare Greater Than Unsigned Hword VCMPGTUHd PPC64LE 000100 vrt:5 vra:5 vrb:5 11001000110 +# format:VC book:I page:397 v3.1 vcmpgtuh[.] Vector Compare Greater Than Unsigned Qword +VCMPGTUQ PPC64LE 000100 vrt:5 vra:5 vrb:5 01010000111 +# format:VC book:I page:397 v3.1 vcmpgtuh[.] Vector Compare Greater Than Unsigned Qword +VCMPGTUQd PPC64LE 000100 vrt:5 vra:5 vrb:5 11010000111 + # format:VC book:I page:311 v2.03 vcmpgtuw[.] Vector Compare Greater Than Unsigned Word VCMPGTUW PPC64LE 000100 vrt:5 vra:5 vrb:5 01010000110 # format:VC book:I page:311 v2.03 vcmpgtuw[.] Vector Compare Greater Than Unsigned Word @@ -2235,6 +2306,28 @@ VCMPNEZW PPC64LE 000100 vrt:5 vra:5 vrb:5 00110000111 # format:VC book:I page:314 v3.0 vcmpnezw[.] Vector Compare Not Equal or Zero Word VCMPNEZWd PPC64LE 000100 vrt:5 vra:5 vrb:5 10110000111 +# format:VC book:I page:401 v3.1 vcmpsq Vector Compare Signed Quadword +VCMPSQ PPC64LE 000100 bf:3 00 vrt:5 vra:5 00101000001 + +# format:VC book:I page:401 v3.1 vcmpsq Vector Compare Unsigned Quadword +VCMPUQ PPC64LE 000100 bf:3 00 vrt:5 vra:5 00100000001 + +# format:VC book:I page:474 v3.1 vcntmbb Vector Count Mask Bits Byte +VCNTMBB PPC64LE 000100 rt:5 1100 mp:1 vrb:5 11001000010 \ +!constraints { $rt != 1 && $rt != 13; } + +# format:VC book:I page:475 v3.1 vcntmbd Vector Count Mask Bits Doubleword +VCNTMBD PPC64LE 000100 rt:5 1111 mp:1 vrb:5 11001000010 \ +!constraints { $rt != 1 && $rt != 13; } + +# format:VC book:I page:474 v3.1 vcntmbh Vector Count Mask Bits Halfword +VCNTMBH PPC64LE 000100 rt:5 1101 mp:1 vrb:5 11001000010 \ +!constraints { $rt != 1 && $rt != 13; } + +# format:VC book:I page:475 v3.1 vcntmbw Vector Count Mask Bits Word +VCNTMBW PPC64LE 000100 rt:5 1110 mp:1 vrb:5 11001000010 \ +!constraints { $rt != 1 && $rt != 13; } + # format:VX book:I page:327 v2.03 vctsxs Vector Convert To Signed Word Saturate VCTSXS PPC64LE 000100 vrt:5 uim:5 vrb:5 01111001010 @@ -2317,6 +2410,10 @@ VEXTUWRX PPC64LE 000100 rt:5 ra:5 vrb:5 11110001101 \ # format:VX book:I page:342 v2.07 vgbbd Vector Gather Bits by Byte by Dword VGBBD PPC64LE 000100 vrt:5 00000 vrb:5 10100001100 +# format:VX book:I page:451 v3.1 vgnb Vector Gather every Nth Bit +VGNB PPC64LE 000100 rt:5 00 n:3 vrb:5 10011001100 \ +!constraints { $rt != 1 && $rt != 13 && $n > 1; } + # format:VX book:I page:270 v3.0 vinsertb Vector Insert Byte VINSERTB PPC64LE 000100 vrt:5 0 uim:4 vrb:5 01100001101 @@ -2422,6 +2519,9 @@ VMRGOW PPC64LE 000100 vrt:5 vra:5 vrb:5 11010001100 # format:VA book:I page:288 v2.03 vmladduhm Vector Multiply-Low-Add Unsigned Hword Modulo VMLADDUHM PPC64LE 000100 vrt:5 vra:5 vrb:5 vrc:5 100010 +# format:VA book:I page:362 v3.1 vmsumcud Vector Multiply-Sum & write Carry-out Unsigned +VMSUMCUD PPC64LE 000100 vrt:5 vra:5 vrb:5 vrc:5 010111 + # format:VA book:I page:289 v2.03 vmsummbm Vector Multiply-Sum Mixed Byte Modulo VMSUMMBM PPC64LE 000100 vrt:5 vra:5 vrb:5 vrc:5 100101 @@ -2434,6 +2534,9 @@ VMSUMSHS PPC64LE 000100 vrt:5 vra:5 vrb:5 vrc:5 101001 # format:VA book:I page:288 v2.03 vmsumubm Vector Multiply-Sum Unsigned Byte Modulo VMSUMUBM PPC64LE 000100 vrt:5 vra:5 vrb:5 vrc:5 100100 +# format:VA book:I page:289 v3.0b vmsumudm Vector Multiply-Sum Unsigned Doubleword Modulo +VMSUMUDM PPC64LE 000100 vrt:5 vra:5 vrb:5 vrc:5 100011 + # format:VA book:I page:290 v2.03 vmsumuhm Vector Multiply-Sum Unsigned Hword Modulo VMSUMUHM PPC64LE 000100 vrt:5 vra:5 vrb:5 vrc:5 100110 @@ -2629,6 +2732,15 @@ VRLDNM PPC64LE 000100 vrt:5 vra:5 vrb:5 00111000101 # format:VX book:I page:318 v2.03 vrlh Vector Rotate Left Hword VRLH PPC64LE 000100 vrt:5 vra:5 vrb:5 00001000100 +# format:VX book:I page:410 v3.1 vrlq Vector Rotate Left Quadword +VRLQ PPC64LE 000100 vrt:5 vra:5 vrb:5 00000000101 + +# format:VX book:I page:417 v3.1 vrlqmi Vector Rotate Left Quadword then Mask Insert +VRLQMI PPC64LE 000100 vrt:5 vra:5 vrb:5 00001000101 + +# format:VX book:I page:414 v3.1 vrlqnm Vector Rotate Left Quadword then AND with Mask +VRLQNM PPC64LE 000100 vrt:5 vra:5 vrb:5 00101000101 + # format:VX book:I page:318 v2.03 vrlw Vector Rotate Left Word VRLW PPC64LE 000100 vrt:5 vra:5 vrb:5 00010000100 @@ -2671,6 +2783,9 @@ VSLH PPC64LE 000100 vrt:5 vra:5 vrb:5 00101000100 # format:VX book:I page:266 v2.03 vslo Vector Shift Left by Octet VSLO PPC64LE 000100 vrt:5 vra:5 vrb:5 10000001100 +# format:VX book:I page:420 v3.1 vslq Vector Shift Left Quadword +VSLQ PPC64LE 000100 vrt:5 vra:5 vrb:5 00100000101 + # format:X book:I page:267 v3.0 vslv Vector Shift Left Variable VSLV PPC64LE 000100 vrt:5 vra:5 vrb:5 11101000100 @@ -2707,6 +2822,9 @@ VSRAD PPC64LE 000100 vrt:5 vra:5 vrb:5 01111000100 # format:VX book:I page:321 v2.03 vsrah Vector Shift Right Algebraic Hword VSRAH PPC64LE 000100 vrt:5 vra:5 vrb:5 01101000100 +# format:VX book:I page:426 v3.1 vsraq Vector Shift Right Algebraic Quadword +VSRAQ PPC64LE 000100 vrt:5 vra:5 vrb:5 01100000101 + # format:VX book:I page:321 v2.03 vsraw Vector Shift Right Algebraic Word VSRAW PPC64LE 000100 vrt:5 vra:5 vrb:5 01110000100 @@ -2716,18 +2834,44 @@ VSRB PPC64LE 000100 vrt:5 vra:5 vrb:5 01000000100 # format:VX book:I page:320 v2.07 vsrd Vector Shift Right Dword VSRD PPC64LE 000100 vrt:5 vra:5 vrb:5 11011000100 +# format:VN boot:I page:299 v3.1 vsrdbi Vector Shift Right Double by Bit Immediate +VSRDBI PPC64LE 000100 vrt:5 vra:5 vrb:5 01 sh:3 010110 + # format:VX book:I page:320 v2.03 vsrh Vector Shift Right Hword VSRH PPC64LE 000100 vrt:5 vra:5 vrb:5 01001000100 # format:VX book:I page:266 v2.03 vsro Vector Shift Right by Octet VSRO PPC64LE 000100 vrt:5 vra:5 vrb:5 10001001100 +# format:VX book:I page:423 v3.1 vsrq Vector Shift Right Quadword +VSRQ PPC64LE 000100 vrt:5 vra:5 vrb:5 01000000101 + # format:X book:I page:267 v3.0 vsrv Vector Shift Right Variable VSRV PPC64LE 000100 vrt:5 vra:5 vrb:5 11100000100 # format:VX book:I page:320 v2.03 vsrw Vector Shift Right Word VSRW PPC64LE 000100 vrt:5 vra:5 vrb:5 01010000100 +# format:VX book:I page:479 v3.1 vstribl Vector String Isolate Byte Left-justified +VSTRIBL PPC64LE 000100 vrt:5 00000 vrb:5 0 0000001101 +# format:VX book:I page:479 v3.1 vstribl. Vector String Isolate Byte Left-justified +VSTRIBLd PPC64LE 000100 vrt:5 00000 vrb:5 1 0000001101 + +# format:VX book:I page:480 v3.1 vstribr Vector String Isolate Byte Right-justified +VSTRIBR PPC64LE 000100 vrt:5 00001 vrb:5 0 0000001101 +# format:VX book:I page:480 v3.1 vstribr. Vector String Isolate Byte Right-justified +VSTRIBRd PPC64LE 000100 vrt:5 00001 vrb:5 1 0000001101 + +# format:VX book:I page:480 v3.1 vstrihl Vector String Isolate Halfword Left-justified +VSTRIHL PPC64LE 000100 vrt:5 00010 vrb:5 0 0000001101 +# format:VX book:I page:480 v3.1 vstrihl. Vector String Isolate Halfword Left-justified +VSTRIHLd PPC64LE 000100 vrt:5 00010 vrb:5 1 0000001101 + +# format:VX book:I page:479 v3.1 vstrihr Vector String Isolate Halfword Right-justified +VSTRIHR PPC64LE 000100 vrt:5 00011 vrb:5 0 0000001101 +# format:VX book:I page:479 v3.1 vstrihr. Vector String Isolate Halfword Right-justified +VSTRIHRd PPC64LE 000100 vrt:5 00011 vrb:5 1 0000001101 + # format:VX book:I page:281 v2.07 vsubcuq Vector Subtract & write Carry Unsigned Qword VSUBCUQ PPC64LE 000100 vrt:5 vra:5 vrb:5 10101000000 @@ -2856,6 +3000,9 @@ XSADDSP PPC64LE 111100 t:5 a:5 b:5 00000000 ax:1 bx:1 tx:1 # format:XX3 book:I page:525 v3.0 xscmpeqdp VSX Scalar Compare Equal Double-Precision XSCMPEQDP PPC64LE 111100 t:5 a:5 b:5 00000011 ax:1 bx:1 tx:1 +# format:X book:I page:679 v3.1 xscmpeqqp VSX Scalar Compare Equal Quad-Precision +XSCMPEQQP PPC64LE 111111 vrt:5 vra:5 vrb:5 0001000100 0 + # format:XX3 book:I page:523 v3.0 xscmpexpdp VSX Scalar Compare Exponents DP XSCMPEXPDP PPC64LE 111100 bf:3 00 a:5 b:5 00111011 ax:1 bx:1 0 @@ -2865,9 +3012,15 @@ XSCMPEXPQP PPC64LE 111111 bf:3 00 vra:5 vrb:5 00101001000 # format:XX3 book:I page:526 v3.0 xscmpgedp VSX Scalar Compare Greater Than or Equal Double-Precision XSCMPGEDP PPC64LE 111100 t:5 a:5 b:5 00010011 ax:1 bx:1 tx:1 +# format:X book:I page:681 v3.1 xscmpgeqp VSX Scalar Compare Greater Than or Equal Quad-Precision +XSCMPGEQP PPC64LE 111111 vrt:5 vra:5 vrb:5 0011000100 0 + # format:XX3 book:I page:527 v3.0 xscmpgtdp VSX Scalar Compare Greater Than Double-Precision XSCMPGTDP PPC64LE 111100 t:5 a:5 b:5 00001011 ax:1 bx:1 tx:1 +# format:X book:I page:683 v3.1 xscmpgtqp VSX Scalar Compare Greater Than Quad-Precision +XSCMPGTQP PPC64LE 111111 vrt:5 vra:5 vrb:5 0011100100 0 + # format:XX3 book:I page:528 v3.0 xscmpnedp VSX Scalar Compare Not Equal Double-Precision XSCMPNEDP PPC64LE 111100 t:5 a:5 b:5 00011011 ax:1 bx:1 tx:1 @@ -2924,12 +3077,18 @@ XSCVQPDPo PPC64LE 111111 vrt:5 10100 vrb:5 11010001001 # format:X book:I page:550 v3.0 xscvqpsdz VSX Scalar Convert QP to Signed Dword truncate XSCVQPSDZ PPC64LE 111111 vrt:5 11001 vrb:5 11010 001000 +# format:X book:I page:707 v3.1 xscvqpsqz VSX Scalar Convert with round to zero Quad-Precision to Signed Quadword +XSCVQPSQZ PPC64LE 111111 vrt:5 01000 vrb:5 1101000100 0 + # format:X book:I page:552 v3.0 xscvqpswz VSX Scalar Convert QP to Signed Word truncate XSCVQPSWZ PPC64LE 111111 vrt:5 01001 vrb:5 11010 001000 # format:X book:I page:554 v3.0 xscvqpudz VSX Scalar Convert QP to Unsigned Dword truncate XSCVQPUDZ PPC64LE 111111 vrt:5 10001 vrb:5 11010 001000 +# format:X book:I page:713 v3.1 xscvqpuqz VSX Scalar Convert with round to zero Quad-Precision to Unsigned Quadword +XSCVQPUQZ PPC64LE 111111 vrt:5 00000 vrb:5 1101000100 0 + # format:X book:I page:556 v3.0 xscvqpuwz VSX Scalar Convert QP to Unsigned Word truncate XSCVQPUWZ PPC64LE 111111 vrt:5 00001 vrb:5 11010 001000 @@ -2942,6 +3101,9 @@ XSCVSPDP PPC64LE 111100 t:5 00000 b:5 10100 1001 bx:1 tx:1 # format:XX2 book:I page:560 v2.07 xscvspdpn VSX Scalar Convert SP to DP Non-signalling XSCVSPDPN PPC64LE 111100 t:5 00000 b:5 10100 1011 bx:1 tx:1 +# format:X book:I page:719 v3.1 xscvsqqp VSX Scalar Convert with round Signed Quadword to Quad-Precision +XSCVSQQP PPC64LE 111111 vrt:5 01011 vrb:5 1101000100 0 + # format:XX2 book:I page:561 v2.06 xscvsxddp VSX Scalar Convert Signed Dword to DP XSCVSXDDP PPC64LE 111100 t:5 00000 b:5 10111 1000 bx:1 tx:1 @@ -2951,6 +3113,9 @@ XSCVSXDSP PPC64LE 111100 t:5 00000 b:5 10011 1000 bx:1 tx:1 # format:X book:I page:562 v3.0 xscvudqp VSX Scalar Convert Unsigned Dword to QP XSCVUDQP PPC64LE 111111 vrt:5 00010 vrb:5 11010 001000 +# format:X book:I page:723 v3.1 xscvuqqp VSX Scalar Convert with round Unsigned Quadword to Quad-Precision +XSCVUQQP PPC64LE 111111 vrt:5 00011 vrb:5 1101000100 0 + # format:XX2 book:I page:563 v2.06 xscvuxddp VSX Scalar Convert Unsigned Dword to DP XSCVUXDDP PPC64LE 111100 t:5 00000 b:5 10110 1000 bx:1 tx:1 @@ -2995,6 +3160,9 @@ XSMADDQPo PPC64LE 111111 vrt:5 vra:5 vrb:5 01100 001001 # format:XX3 book:I page:583 v3.0 xsmaxcdp VSX Scalar Maximum Type-C Double-Precision XSMAXCDP PPC64LE 111100 t:5 a:5 b:5 10000000 ax:1 bx:1 tx:1 +# format:X book:I page:746 v3.1 xsmaxcqp VSX Scalar Maximum Type-C Quad-Precision +XSMAXCQP PPC64LE 111111 vrt:5 vra:5 vrb:5 1010100100 0 + # format:XX3 book:I page:581 v2.06 xsmaxdp VSX Scalar Maximum DP XSMAXDP PPC64LE 111100 t:5 a:5 b:5 10100000 ax:1 bx:1 tx:1 @@ -3004,6 +3172,9 @@ XMAXJDP PPC64LE 111100 t:5 a:5 b:5 10010000 ax:1 bx:1 tx:1 # format:XX3 book:I page:589 v3.0 xsmincdp VSX Scalar Minimum Type-C Double-Precision XSMINCDP PPC64LE 111100 t:5 a:5 b:5 10001000 ax:1 bx:1 tx:1 +# format:X book:I page:754 v3.1 xsmincqp VSX Scalar Minimum Type-C Quad-Precision +XSMINCQP PPC64LE 111111 vrt:5 vra:5 vrb:5 1011100100 0 + # format:XX3 book:I page:587 v2.06 xsmindp VSX Scalar Minimum DP XSMINDP PPC64LE 111100 t:5 a:5 b:5 10101000 ax:1 bx:1 tx:1 @@ -3445,6 +3616,9 @@ XVTDIVDP PPC64LE 111100 bf:3 00 a:5 b:5 01111101 ax:1 bx:1 0 # format:XX3 book:I page:762 v2.06 xvtdivsp VSX Vector Test for software Divide SP XVTDIVSP PPC64LE 111100 bf:3 00 a:5 b:5 01011101 ax:1 bx:1 0 +# format:XX2 book:I page:968 v3.1 xvtlsbb VSX Vector Test Least-Significant Bit by Byte +XVTLSBB PPC64LE 111100 bf:3 00 00010 b:5 111011011 bx:1 0 + # format:XX2 book:I page:763 v2.06 xvtsqrtdp VSX Vector Test for software Square Root DP XVTSQRTDP PPC64LE 111100 bf:3 0000000 b:5 011101010 bx:1 0 @@ -3484,6 +3658,18 @@ XXBRW PPC64LE 111100 t:5 01111 b:5 111011011 bx:1 tx:1 # format:XX2 book:I page:770 v3.0 xxextractuw VSX Vector Extract Unsigned Word XXEXTRACTUW PPC64LE 111100 t:5 0 uim:4 b:5 010100101 bx:1 tx:1 +# format:X book:I page:979 v3.1 xxgenpcvbm VSX Vector Generate PCV from Byte Mask +XXGENPCVBM PPC64LE 111100 t:5 000 imm:2 vrb:5 1110010100 tx:1 + +# format:X book:I page:985 v3.1 xxgenpcvdm VSX Vector Generate PCV from Doubleword Mask +XXGENPCVDM PPC64LE 111100 t:5 000 imm:2 vrb:5 1110110101 tx:1 + +# format:X book:I page:981 v3.1 xxgenpcvhm VSX Vector Generate PCV from Halfword Mask +XXGENPCVHM PPC64LE 111100 t:5 000 imm:2 vrb:5 1110010101 tx:1 + +# format:X book:I page:983 v3.1 xxgenpcvwm VSX Vector Generate PCV from Word Mask +XXGENPCVWM PPC64LE 111100 t:5 000 imm:2 vrb:5 1110110100 tx:1 + # format:XX2 book:I page:770 v3.0 xxinsertw VSX Vector Insert Word XXINSERTW PPC64LE 111100 t:5 0 uim:4 b:5 010110101 bx:1 tx:1 From 8a876af30ccc9066f86b232d377b4b82491b9e43 Mon Sep 17 00:00:00 2001 From: "Lucas Mateus Castro (alqotel)" Date: Mon, 31 Oct 2022 15:40:44 -0300 Subject: [PATCH 18/22] ppc64: more POWER10 insns --- ppc64.risu | 177 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/ppc64.risu b/ppc64.risu index e8a2f48..8691c77 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -2350,6 +2350,42 @@ VCTZLSBB PPC64LE 000100 rt:5 00001 vrb:5 11000000010 \ # format:VX book:I page:344 v3.0 vctzw Vector Count Trailing Zeros Word VCTZW PPC64LE 000100 vrt:5 11110 vrb:5 11000000010 +# format:VX book:I page 361 v3.1 vdivesd Vector Divide Extended Signed Doubleword +VDIVESD PPC64LE 000100 vrt:5 vra:5 vrb:5 01111001011 + +# format:VX book:I page 363 v3.1 vdivesq Vector Divide Extended Signed Quadword +VDIVESQ PPC64LE 000100 vrt:5 vra:5 vrb:5 01100001011 + +# format:VX book:I page 359 v3.1 vdivesw Vector Divide Extended Signed Word +VDIVESW PPC64LE 000100 vrt:5 vra:5 vrb:5 01110001011 + +# format:VX book:I page 361 v3.1 vdiveud Vector Divide Extended Unsigned Doubleword +VDIVEUD PPC64LE 000100 vrt:5 vra:5 vrb:5 01011001011 + +# format:VX book:I page 363 v3.1 vdiveuq Vector Divide Extended Unsigned Quadword +VDIVEUQ PPC64LE 000100 vrt:5 vra:5 vrb:5 01000001011 + +# format:VX book:I page 359 v3.1 vdiveuw Vector Divide Extended Unsigned Word +VDIVEUW PPC64LE 000100 vrt:5 vra:5 vrb:5 01010001011 + +# format:VX book:I page 360 v3.1 vdivsd Vector Divide Signed Doubleword +VDIVSD PPC64LE 000100 vrt:5 vra:5 vrb:5 00111001011 + +# format:VX book:I page 362 v3.1 vdivsq Vector Divide Signed Quadword +VDIVSQ PPC64LE 000100 vrt:5 vra:5 vrb:5 00100001011 + +# format:VX book:I page 358 v3.1 vdivsw Vector Divide Signed Word +VDIVSW PPC64LE 000100 vrt:5 vra:5 vrb:5 00110001011 + +# format:VX book:I page 360 v3.1 vdivud Vector Divide Unsigned Doubleword +VDIVUD PPC64LE 000100 vrt:5 vra:5 vrb:5 00011001011 + +# format:VX book:I page 362 v3.1 vdivuq Vector Divide Unsigned Quadword +VDIVUQ PPC64LE 000100 vrt:5 vra:5 vrb:5 00000001011 + +# format:VX book:I page 358 v3.1 vdivuw Vector Divide Unsigned Word +VDIVUW PPC64LE 000100 vrt:5 vra:5 vrb:5 00010001011 + # format:VX book:I page:315 v2.07 veqv Vector Logical Equivalence VEQV PPC64LE 000100 vrt:5 vra:5 vrb:5 11010000100 @@ -2492,6 +2528,24 @@ VMINUH PPC64LE 000100 vrt:5 vra:5 vrb:5 01001000010 # format:VX book:I page:305 v2.03 vminuw Vector Minimum Unsigned Word VMINUW PPC64LE 000100 vrt:5 vra:5 vrb:5 01010000010 +# format:VX book:I page 365 v3.1 vmodsd Vector Modulo Signed Doubleword +VMODSD PPC64LE 000100 vrt:5 vra:5 vrb:5 11111001011 + +# format:VX book:I page 366 v3.1 vmodsq Vector Modulo Signed Quadword +VMODSQ PPC64LE 000100 vrt:5 vra:5 vrb:5 11100001011 + +# format:VX book:I page 364 v3.1 vmodsw Vector Modulo Signed Word +VMODSW PPC64LE 000100 vrt:5 vra:5 vrb:5 11110001011 + +# format:VX book:I page 365 v3.1 vmodud Vector Modulo Unsigned Doubleword +VMODUD PPC64LE 000100 vrt:5 vra:5 vrb:5 11011001011 + +# format:VX book:I page 366 v3.1 vmoduq Vector Modulo Unsigned Quadword +VMODUQ PPC64LE 000100 vrt:5 vra:5 vrb:5 11000001011 + +# format:VX book:I page 364 v3.1 vmoduw Vector Modulo Unsigned Word +VMODUW PPC64LE 000100 vrt:5 vra:5 vrb:5 11010001011 + # format:VX book:I page:259 v2.07 vmrgew Vector Merge Even Word VMRGEW PPC64LE 000100 vrt:5 vra:5 vrb:5 11110001100 @@ -2558,6 +2612,9 @@ VMUL10UQ PPC64LE 000100 vrt:5 vra:5 0000001000000001 # format:VX book:I page:283 v2.03 vmulesb Vector Multiply Even Signed Byte VMULESB PPC64LE 000100 vrt:5 vra:5 vrb:5 01100001000 +# format:VX book:I page 345 v3.1 vmulesd Vector Multiply Even Signed Doubleword +VMULESD PPC64LE 000100 vrt:5 vra:5 vrb:5 01111001000 + # format:VX book:I page:284 v2.03 vmulesh Vector Multiply Even Signed Hword VMULESH PPC64LE 000100 vrt:5 vra:5 vrb:5 01101001000 @@ -2567,15 +2624,36 @@ VMULESW PPC64LE 000100 vrt:5 vra:5 vrb:5 01110001000 # format:VX book:I page:283 v2.03 vmuleub Vector Multiply Even Unsigned Byte VMULEUB PPC64LE 000100 vrt:5 vra:5 vrb:5 01000001000 +# format:VX book:I page 346 v3.1 vmuleud Vector Multiply Even Unsigned Doubleword +VMULEUD PPC64LE 000100 vrt:5 vra:5 vrb:5 01011001000 + # format:VX book:I page:284 v2.03 vmuleuh Vector Multiply Even Unsigned Hword VMULEUH PPC64LE 000100 vrt:5 vra:5 vrb:5 01001001000 # format:VX book:I page:285 v2.07 vmuleuw Vector Multiply Even Unsigned Word VMULEUW PPC64LE 000100 vrt:5 vra:5 vrb:5 01010001000 +# format:VX book:I page 349 v3.1 vmulhsd Vector Multiply High Signed Doubleword +VMULHSD PPC64LE 000100 vrt:5 vra:5 vrb:5 01111001001 + +# format:VX book:I page 347 v3.1 vmulhsw Vector Multiply High Signed Word +VMULHSW PPC64LE 000100 vrt:5 vra:5 vrb:5 01110001001 + +# format:VX book:I page 349 v3.1 vmulhud Vector Multiply High Unsigned Doubleword +VMULHUD PPC64LE 000100 vrt:5 vra:5 vrb:5 01011001001 + +# format:VX book:I page 348 v3.1 vmulhuw Vector Multiply High Unsigned Word +VMULHUW PPC64LE 000100 vrt:5 vra:5 vrb:5 01010001001 + +# format:VX book:I page 350 v3.1 vmulld Vector Multiply Low Doubleword +VMULLD PPC64LE 000100 vrt:5 vra:5 vrb:5 00111001001 + # format:VX book:I page:283 v2.03 vmulosb Vector Multiply Odd Signed Byte VMULOSB PPC64LE 000100 vrt:5 vra:5 vrb:5 00100001000 +# format:VX book:I page 345 v3.1 vmulosd Vector Multiply Odd Signed Doubleword +VMULOSD PPC64LE 000100 vrt:5 vra:5 vrb:5 00111001000 + # format:VX book:I page:284 v2.03 vmulosh Vector Multiply Odd Signed Hword VMULOSH PPC64LE 000100 vrt:5 vra:5 vrb:5 00101001000 @@ -2585,6 +2663,9 @@ VMULOSW PPC64LE 000100 vrt:5 vra:5 vrb:5 00110001000 # format:VX book:I page:283 v2.03 vmuloub Vector Multiply Odd Unsigned Byte VMULOUB PPC64LE 000100 vrt:5 vra:5 vrb:5 00000001000 +# format:VX book:I page 346 v3.1 vmuloud Vector Multiply Odd Unsigned Doubleword +VMULOUD PPC64LE 000100 vrt:5 vra:5 vrb:5 00011001000 + # format:VX book:I page:284 v2.03 vmulouh Vector Multiply Odd Unsigned Hword VMULOUH PPC64LE 000100 vrt:5 vra:5 vrb:5 00001001000 @@ -3359,6 +3440,21 @@ XVADDDP PPC64LE 111100 t:5 a:5 b:5 01100000 ax:1 bx:1 tx:1 # format:XX3 book:I page:665 v2.06 xvaddsp VSX Vector Add SP XVADDSP PPC64LE 111100 t:5 a:5 b:5 01000000 ax:1 bx:1 tx:1 +# format:XX3 book:I page:827 v3.01 xvbf16ger2 VSX Vector bfloat16 GER (rank-2 update) +XVBF16GER2 PPC64LE 111011 at:3 00 a:5 b:5 00110011 ax:1 bx:1 0 + +# format:XX3 book:I page:827 v3.01 xvbf16ger2nn VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Negative accumulate +XVBF16GER2NN PPC64LE 111011 at:3 00 a:5 b:5 11110010 ax:1 bx:1 0 + +# format:XX3 book:I page:827 v3.01 xvbf16ger2np VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Positive accumulate +XVBF16GER2NP PPC64LE 111011 at:3 00 a:5 b:5 01110010 ax:1 bx:1 0 + +# format:XX3 book:I page:827 v3.01 xvbf16ger2pn VSX Vector bfloat16 GER (rank-2 update) Positive multiply, Negative accumulate +XVBF16GER2PN PPC64LE 111011 at:3 00 a:5 b:5 10110010 ax:1 bx:1 0 + +# format:XX3 book:I page:827 v3.01 xvbf16ger2pp VSX Vector bfloat16 GER (rank-2 update) Positive multiply, Positive accumulate +XVBF16GER2PP PPC64LE 111011 at:3 00 a:5 b:5 00110010 ax:1 bx:1 0 + # format:XX3 book:I page:667 v2.06 xvcmpeqdp[.] VSX Vector Compare Equal DP XVCMPEQDP PPC64LE 111100 t:5 a:5 b:5 01100011 ax:1 bx:1 tx:1 # format:XX3 book:I page:667 v2.06 xvcmpeqdp[.] VSX Vector Compare Equal DP @@ -3472,6 +3568,78 @@ XVDIVDP PPC64LE 111100 t:5 a:5 b:5 01111000 ax:1 bx:1 tx:1 # format:XX3 book:I page:702 v2.06 xvdivsp VSX Vector Divide SP XVDIVSP PPC64LE 111100 t:5 a:5 b:5 01011000 ax:1 bx:1 tx:1 +# format:XX3 book:I page:871 v3.01 xvf16ger2 VSX Vector 16-bit Floating-Point GER (rank-2 update) +XVF16GER2 PPC64LE 111011 at:3 00 a:5 b:5 00010011 ax:1 bx:1 0 + +# format:XX3 book:I page:871 v3.01 xvf16ger2nn VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate +XVF16GER2NN PPC64LE 111011 at:3 00 a:5 b:5 11010010 ax:1 bx:1 0 + +# format:XX3 book:I page:871 v3.01 xvf16ger2np VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate +XVF16GER2NP PPC64LE 111011 at:3 00 a:5 b:5 01010010 ax:1 bx:1 0 + +# format:XX3 book:I page:871 v3.01 xvf16ger2pn VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate +XVF16GER2PN PPC64LE 111011 at:3 00 a:5 b:5 10010010 ax:1 bx:1 0 + +# format:XX3 book:I page:871 v3.01 xvf16ger2pp VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate +XVF16GER2PP PPC64LE 111011 at:3 00 a:5 b:5 00010010 ax:1 bx:1 0 + +# format:XX3 book:I page:875 v3.01 xvf32ger VSX Vector 32-bit Floating-Point GER (rank-1 update) +XVF32GER PPC64LE 111011 at:3 00 a:5 b:5 00011011 ax:1 bx:1 0 + +# format:XX3 book:I page:875 v3.01 xvf32gernn VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate +XVF32GERNN PPC64LE 111011 at:3 00 a:5 b:5 11011010 ax:1 bx:1 0 + +# format:XX3 book:I page:875 v3.01 xvf32gernp VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate +XVF32GERNP PPC64LE 111011 at:3 00 a:5 b:5 01011010 ax:1 bx:1 0 + +# format:XX3 book:I page:875 v3.01 xvf32gerpn VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate +XVF32GERPN PPC64LE 111011 at:3 00 a:5 b:5 10011010 ax:1 bx:1 0 + +# format:XX3 book:I page:875 v3.01 xvf32gerpp VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate +XVF32GERPP PPC64LE 111011 at:3 00 a:5 b:5 00011010 ax:1 bx:1 0 + +# format:XX3 book:I page:879 v3.01 xvf64ger VSX Vector 64-bit Floating-Point GER (rank-1 update) +XVF64GER PPC64LE 111011 at:3 00 a:4 0 b:5 00111011 ax:1 bx:1 0 + +# format:XX3 book:I page:879 v3.01 xvf64gernn VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate +XVF64GERNN PPC64LE 111011 at:3 00 a:4 0 b:5 11111010 ax:1 bx:1 0 + +# format:XX3 book:I page:879 v3.01 xvf64gernp VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate +XVF64GERNP PPC64LE 111011 at:3 00 a:4 0 b:5 01111010 ax:1 bx:1 0 + +# format:XX3 book:I page:879 v3.01 xvf64gerpn VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate +XVF64GERPN PPC64LE 111011 at:3 00 a:4 0 b:5 10111010 ax:1 bx:1 0 + +# format:XX3 book:I page:879 v3.01 xvf64gerpp VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate +XVF64GERPP PPC64LE 111011 at:3 00 a:4 0 b:5 00111010 ax:1 bx:1 0 + +# format:XX3 book:I page:891 v3.01 xvi16ger2 VSX Vector 16-bit Signed Integer GER (rank-2 update) +XVI16GER2 PPC64LE 111011 at:3 00 a:5 b:5 01001011 ax:1 bx:1 0 + +# format:XX3 book:I page:891 v3.01 xvi16ger2 VSX Vector 16-bit Signed Integer GER (rank-2 update) +XVI16GER2PP PPC64LE 111011 at:3 00 a:5 b:5 01101011 ax:1 bx:1 0 + +# format:XX3 book:I page:891 v3.01 xvi16ger2s VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate +XVI16GER2S PPC64LE 111011 at:3 00 a:5 b:5 00101011 ax:1 bx:1 0 + +# format:XX3 book:I page:891 v3.01 xvi16ger2 VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate +XVI16GER2SPP PPC64LE 111011 at:3 00 a:5 b:5 00101010 ax:1 bx:1 0 + +# format:XX3 book:I page:883 v3.01 xvi4ger8 VSX Vector 4-bit Signed Integer GER (rank-8 update) +XVI4GER8 PPC64LE 111011 at:3 00 a:5 b:5 00100011 ax:1 bx:1 0 + +# format:XX3 book:I page:883 v3.01 xvi4ger8pp VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate +XVI4GER8PP PPC64LE 111011 at:3 00 a:5 b:5 00100010 ax:1 bx:1 0 + +# format:XX3 book:I page:886 v3.01 xvi8ger4 VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) +XVI8GER4 PPC64LE 111011 at:3 00 a:5 b:5 00000011 ax:1 bx:1 0 + +# format:XX3 book:I page:886 v3.01 xvi8ger4pp VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate +XVI8GER4PP PPC64LE 111011 at:3 00 a:5 b:5 00000010 ax:1 bx:1 0 + +# format:XX3 book:I page:889 v3.01 xvi8ger4spp VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate +XVI8GER4SPP PPC64LE 111011 at:3 00 a:5 b:5 01100011 ax:1 bx:1 0 + # format:XX3 book:I page:704 v3.0 xviexpdp VSX Vector Insert Exponent DP XVIEXPDP PPC64LE 111100 t:5 a:5 b:5 11111000 ax:1 bx:1 tx:1 @@ -3697,12 +3865,18 @@ XXLORC PPC64LE 111100 t:5 a:5 b:5 10101010 ax:1 bx:1 tx:1 # format:XX3 book:I page:774 v2.06 xxlxor VSX Vector Logical XOR XXLXOR PPC64LE 111100 t:5 a:5 b:5 10011010 ax:1 bx:1 tx:1 +# format:X book:I page 983 v3.1 xxmfacc VSX Move From Accumulator +XXMFACC PPC64LE 011111 as:3 00 00000 00000 0010110001 0 + # format:XX3 book:I page:775 v2.06 xxmrghw VSX Vector Merge Word High XXMRGHW PPC64LE 111100 t:5 a:5 b:5 00010010 ax:1 bx:1 tx:1 # format:XX3 book:I page:775 v2.06 xxmrglw VSX Vector Merge Word Low XXMRGLW PPC64LE 111100 t:5 a:5 b:5 00110010 ax:1 bx:1 tx:1 +# format:X book:I page 984 v3.1 xxmtacc VSX Move To Accumulator +XXMTACC PPC64LE 011111 at:3 00 00001 00000 0010110001 0 + # format:XX3 book:I page:776 v3.0 xxperm VSX Vector Permute XXPERM PPC64LE 111100 t:5 a:5 b:5 00011010 ax:1 bx:1 tx:1 @@ -3715,6 +3889,9 @@ XXPERMR PPC64LE 111100 t:5 a:5 b:5 00111010 ax:1 bx:1 tx:1 # format:XX4 book:I page:777 v2.06 xxsel VSX Vector Select XXSEL PPC64LE 111100 t:5 a:5 b:5 c:5 11 cx:1 ax:1 bx:1 tx:1 +# format:X book:I page 989 v3.1 xxsetaccz VSX Set Accumulator to Zero +XXSETACCZ PPC64LE 011111 at:3 00 00011 00000 0010110001 0 + # format:XX3 book:I page:778 v2.06 xxsldwi VSX Vector Shift Left Double by Word Immediate XXSLDWI PPC64LE 111100 t:5 a:5 b:5 0 shw:2 00010 ax:1 bx:1 tx:1 From 45b7239df2399c9b9e456992e71e55cc73bd01c3 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Wed, 12 Jan 2022 16:10:01 -0300 Subject: [PATCH 19/22] ppc64: add support to prefixed insns Works for PPC64, seems to work for m68k, but still breaks ARM. --- risugen | 9 ++++++--- risugen_arm.pm | 3 ++- risugen_m68k.pm | 3 ++- risugen_ppc64.pm | 16 ++++++++++++++-- 4 files changed, 24 insertions(+), 7 deletions(-) diff --git a/risugen b/risugen index 586bb8f..9b8a53f 100755 --- a/risugen +++ b/risugen @@ -162,8 +162,8 @@ sub parse_config_file($) my $fixedbits = 0; my $fixedbitmask = 0; - my $bitpos = 32; - my $insnwidth = 32; + my $bitpos = 64; + my $insnwidth = 64; my $seenblock = 0; while (@bits) { @@ -229,7 +229,10 @@ sub parse_config_file($) push @fields, [ $var, $bitpos, $bitmask ]; } } - if ($bitpos == 16) { + if ($bitpos == (64 - 32)) { + # normal/non-prefixed instruction + $insnwidth = 32; + } elsif ($bitpos == (64 - 16)) { # assume this is a half-width thumb instruction # Note that we don't fiddle with the bitmasks or positions, # which means the generated insn will be in the high halfword! diff --git a/risugen_arm.pm b/risugen_arm.pm index 8d423b1..2147017 100644 --- a/risugen_arm.pm +++ b/risugen_arm.pm @@ -961,7 +961,7 @@ sub gen_one_insn($$) INSN: while(1) { my ($forcecond, $rec) = @_; - my $insn = int(rand(0xffffffff)); + my $insn = int(rand(0xffffffff)) << 32; my $insnname = $rec->{name}; my $insnwidth = $rec->{width}; my $fixedbits = $rec->{fixedbits}; @@ -1005,6 +1005,7 @@ sub gen_one_insn($$) # OK, we got a good one $constraintfailures = 0; + $insn >>= 32; my $basereg; diff --git a/risugen_m68k.pm b/risugen_m68k.pm index 7d62b13..b999f69 100644 --- a/risugen_m68k.pm +++ b/risugen_m68k.pm @@ -108,7 +108,7 @@ sub gen_one_insn($$) INSN: while(1) { my ($forcecond, $rec) = @_; - my $insn = int(rand(0xffffffff)); + my $insn = int(rand(0xffffffff)) << 32; my $insnname = $rec->{name}; my $insnwidth = $rec->{width}; my $fixedbits = $rec->{fixedbits}; @@ -142,6 +142,7 @@ sub gen_one_insn($$) # OK, we got a good one $constraintfailures = 0; + $insn >>= 32; insn16($insn >> 16); if ($insnwidth == 32) { diff --git a/risugen_ppc64.pm b/risugen_ppc64.pm index 5fcb55c..3db39bb 100644 --- a/risugen_ppc64.pm +++ b/risugen_ppc64.pm @@ -338,7 +338,7 @@ sub gen_one_insn($$) INSN: while(1) { my ($forcecond, $rec) = @_; - my $insn = int(rand(0xffffffff)); + my $insn = int(rand(0xffffffff)) << 32 | int(rand(0xffffffff)); my $insnname = $rec->{name}; my $insnwidth = $rec->{width}; my $fixedbits = $rec->{fixedbits}; @@ -379,7 +379,19 @@ sub gen_one_insn($$) $basereg = eval_with_fields($insnname, $insn, $rec, "memory", $memblock); } - insn32($insn); + if ($insnwidth == 64) { + if((($bytecount+4) & 63) == 0) { + # Power v3.1, section 1.9 Exceptions: + # attempt to execute a prefixed instruction that crosses a + # 64-byte address boundary (system alignment error). + # Emit a NOP before the next prefixed instruction + insn32(0x60000000); + } + insn32($insn >> 32); + insn32($insn & 0xffffffff); + } else { + insn32($insn >> 32); + } if (defined $memblock) { # Clean up following a memory access instruction: From d382ac2d4a038c4a5e9ff6dd4b81f53c2148c2b3 Mon Sep 17 00:00:00 2001 From: Matheus Ferst Date: Mon, 31 Oct 2022 15:50:21 -0300 Subject: [PATCH 20/22] ppc64: prefixed insns examples --- ppc64.risu | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/ppc64.risu b/ppc64.risu index 8691c77..bddbf01 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -1530,6 +1530,10 @@ ORI PPC64LE 011000 rs:5 ra:5 imm:16 \ ORIS PPC64LE 011001 rs:5 ra:5 imm:16 \ !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } +# format:MLS-D book:I page:78 v3.1 paddi Prefixed Add Immediate +PADDI PPC64LE 000001 10 000 r:1 00 si0:18 001110 rt:5 ra:5 si1:16 \ +!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; } + # format:X book:I page:96 v2.02 popcntb Population Count Byte POPCNTB PPC64LE 011111 rs:5 ra:5 0000000011110100 \ !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } @@ -3823,6 +3827,10 @@ XXBRQ PPC64LE 111100 t:5 11111 b:5 111011011 bx:1 tx:1 # format:XX2 book:I page:769 v3.0 xxbrw VSX Vector Byte-Reverse Word XXBRW PPC64LE 111100 t:5 01111 b:5 111011011 bx:1 tx:1 +# format:8RR-XX4 book:I page:976 v3.1 xxeval VSX Vector Evaluate +XXEVAL PPC64LE 000001 01 0000 00 0000000000 imm:8 \ + 100010 t:5 a:5 b:5 c:5 01 cx:1 ax:1 bx:1 tx:1 + # format:XX2 book:I page:770 v3.0 xxextractuw VSX Vector Extract Unsigned Word XXEXTRACTUW PPC64LE 111100 t:5 0 uim:4 b:5 010100101 bx:1 tx:1 @@ -3886,6 +3894,10 @@ XXPERMDI PPC64LE 111100 t:5 a:5 b:5 0 dm:2 01010 ax:1 bx:1 tx:1 # format:XX3 book:I page:776 v3.0 xxpermr VSX Vector Permute Right-indexed XXPERMR PPC64LE 111100 t:5 a:5 b:5 00111010 ax:1 bx:1 tx:1 +# format:8RR-XX4 book:I page:997 xxpermx VSX Vector Permute Extended +XXPERMX PPC64LE 000001 01 0000 00 000000000000000 uim:3 \ + 100010 t:5 a:5 b:5 c:5 00 cx:1 ax:1 bx:1 tx:1 + # format:XX4 book:I page:777 v2.06 xxsel VSX Vector Select XXSEL PPC64LE 111100 t:5 a:5 b:5 c:5 11 cx:1 ax:1 bx:1 tx:1 From 0afdbd86962cf6dd99e79a44ee6907c4337abb20 Mon Sep 17 00:00:00 2001 From: "Lucas Mateus Castro (alqotel)" Date: Mon, 31 Oct 2022 15:53:13 -0300 Subject: [PATCH 21/22] ppc64: MMA prefixed insns patterns --- ppc64.risu | 116 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) diff --git a/ppc64.risu b/ppc64.risu index bddbf01..abf6077 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -1534,6 +1534,122 @@ ORIS PPC64LE 011001 rs:5 ra:5 imm:16 \ PADDI PPC64LE 000001 10 000 r:1 00 si0:18 001110 rt:5 ra:5 si1:16 \ !constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; } +# format:XX3 book:I page:827 v3.01 xvbf16ger2 Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) +PMXVBF16GER2 PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00110011 ax:1 bx:1 0 + +# format:XX3 book:I page:827 v3.01 xvbf16ger2nn Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Negative accumulate +PMXVBF16GER2NN PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 11110010 ax:1 bx:1 0 + +# format:XX3 book:I page:827 v3.01 xvbf16ger2np Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) Negative multiply, Positive accumulate +PMXVBF16GER2NP PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 01110010 ax:1 bx:1 0 + +# format:XX3 book:I page:827 v3.01 xvbf16ger2pn Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) Positive multiply, Negative accumulate +PMXVBF16GER2PN PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 10110010 ax:1 bx:1 0 + +# format:XX3 book:I page:827 v3.01 xvbf16ger2pp Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) Positive multiply, Positive accumulate +PMXVBF16GER2PP PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00110010 ax:1 bx:1 0 + +# format:XX3 book:I page:891 v3.01 xvi16ger2 Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) +PMXVI16GER2 PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 01001011 ax:1 bx:1 0 + +# format:XX3 book:I page:891 v3.01 xvi16ger2 Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) +PMXVI16GER2PP PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 01101011 ax:1 bx:1 0 + +# format:XX3 book:I page:891 v3.01 xvi16ger2s Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate +PMXVI16GER2S PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00101011 ax:1 bx:1 0 + +# format:XX3 book:I page:891 v3.01 xvi16ger2 Prefixed Masked VSX Vector 16-bit Signed Integer GER (rank-2 update) with Saturation Positive multiply, Positive accumulate +PMXVI16GER2SPP PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00101010 ax:1 bx:1 0 + +# format:XX3 book:I page:883 v3.01 xvi4ger8 Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) +PMXVI4GER8 PPC64LE 000001 11 1001 00 0 0 pmsk:8 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00100011 ax:1 bx:1 0 + +# format:XX3 book:I page:883 v3.01 xvi4ger8pp Prefixed Masked VSX Vector 4-bit Signed Integer GER (rank-8 update) Positive multiply, Positive accumulate +PMXVI4GER8PP PPC64LE 000001 11 1001 00 0 0 pmsk:8 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00100010 ax:1 bx:1 0 + +# format:XX3 book:I page:886 v3.01 xvi8ger4 Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) +PMXVI8GER4 PPC64LE 000001 11 1001 00 0 0 pmsk:4 0000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00000011 ax:1 bx:1 0 + +# format:XX3 book:I page:886 v3.01 xvi8ger4pp Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) Positive multiply, Positive accumulate +PMXVI8GER4PP PPC64LE 000001 11 1001 00 0 0 pmsk:4 0000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00000010 ax:1 bx:1 0 + +# format:XX3 book:I page:889 v3.01 xvi8ger4spp Prefixed Masked VSX Vector 8-bit Signed/Unsigned Integer GER (rank-4 update) with Saturate Positive multiply, Positive accumulate +PMXVI8GER4SPP PPC64LE 000001 11 1001 00 0 0 pmsk:4 0000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 01100011 ax:1 bx:1 0 + +# format:XX3 book:I page:871 v3.01 xvf16ger2 Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) +PMXVF16GER2 PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00010011 ax:1 bx:1 0 + +# format:XX3 book:I page:871 v3.01 xvf16ger2nn Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Negative accumulate +PMXVF16GER2NN PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 11010010 ax:1 bx:1 0 + +# format:XX3 book:I page:871 v3.01 xvf16ger2np Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Negative multiply, Positive accumulate +PMXVF16GER2NP PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 01010010 ax:1 bx:1 0 + +# format:XX3 book:I page:871 v3.01 xvf16ger2pn Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Negative accumulate +PMXVF16GER2PN PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 10010010 ax:1 bx:1 0 + +# format:XX3 book:I page:871 v3.01 xvf16ger2pp Prefixed Masked VSX Vector 16-bit Floating-Point GER (rank-2 update) Positive multiply, Positive accumulate +PMXVF16GER2PP PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00010010 ax:1 bx:1 0 + +# format:XX3 book:I page:875 v3.01 xvf32ger Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) +PMXVF32GER PPC64LE 000001 11 1001 00 0 0 00000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00011011 ax:1 bx:1 0 + +# format:XX3 book:I page:875 v3.01 xvf32gernn Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate +PMXVF32GERNN PPC64LE 000001 11 1001 00 0 0 00000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 11011010 ax:1 bx:1 0 + +# format:XX3 book:I page:875 v3.01 xvf32gernp Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate +PMXVF32GERNP PPC64LE 000001 11 1001 00 0 0 00000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 01011010 ax:1 bx:1 0 + +# format:XX3 book:I page:875 v3.01 xvf32gerpn Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate +PMXVF32GERPN PPC64LE 000001 11 1001 00 0 0 00000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 10011010 ax:1 bx:1 0 + +# format:XX3 book:I page:875 v3.01 xvf32gerpp Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate +PMXVF32GERPP PPC64LE 000001 11 1001 00 0 0 00000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:5 b:5 00011010 ax:1 bx:1 0 + +# format:XX3 book:I page:879 v3.01 xvf64ger Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) +PMXVF64GER PPC64LE 000001 11 1001 00 0 0 00000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:4 0 b:5 00111011 ax:1 bx:1 0 + +# format:XX3 book:I page:879 v3.01 xvf64gernn Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Negative accumulate +PMXVF64GERNN PPC64LE 000001 11 1001 00 0 0 00000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:4 0 b:5 11111010 ax:1 bx:1 0 + +# format:XX3 book:I page:879 v3.01 xvf64gernp Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate +PMXVF64GERNP PPC64LE 000001 11 1001 00 0 0 00000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:4 0 b:5 01111010 ax:1 bx:1 0 + +# format:XX3 book:I page:879 v3.01 xvf64gerpn Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Negative accumulate +PMXVF64GERPN PPC64LE 000001 11 1001 00 0 0 00000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:4 0 b:5 10111010 ax:1 bx:1 0 + +# format:XX3 book:I page:879 v3.01 xvf64gerpp Prefixed Masked VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive multiply, Positive accumulate +PMXVF64GERPP PPC64LE 000001 11 1001 00 0 0 00000000 xmks:4 ymsk:4 \ + 111011 at:3 00 a:4 0 b:5 00111010 ax:1 bx:1 0 + # format:X book:I page:96 v2.02 popcntb Population Count Byte POPCNTB PPC64LE 011111 rs:5 ra:5 0000000011110100 \ !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } From de8c5e7ca576f27ff7793ad69ebb4681d62b6428 Mon Sep 17 00:00:00 2001 From: Leandro Lupori Date: Mon, 31 Oct 2022 16:03:00 -0300 Subject: [PATCH 22/22] ppc64: add plxsd/pstxsd and plxssp/pstxssp --- ppc64.risu | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/ppc64.risu b/ppc64.risu index abf6077..2f07fd7 100644 --- a/ppc64.risu +++ b/ppc64.risu @@ -1534,6 +1534,20 @@ ORIS PPC64LE 011001 rs:5 ra:5 imm:16 \ PADDI PPC64LE 000001 10 000 r:1 00 si0:18 001110 rt:5 ra:5 si1:16 \ !constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13; } +# format:8LS:D book:I page:618 v3.1B plxsd Prefixed Load VSX Scalar Doubleword +PLXSD PPC64LE 000001 00000 0 00 d0:18 \ + 101010 rt:5 ra:5 d1:16 \ +!constraints { $ra != 0 && $ra != 1 && $ra != 13 && \ + $d0 <= 65535 && $d1 <= 32767 } \ +!memory { reg_plus_imm($ra, ($d0 << 16) | $d1); } + +# format:8LS:D book:I page:623 v3.1B plxssp Prefixed Load VSX Scalar Single-Precision +PLXSSP PPC64LE 000001 00000 0 00 d0:18 \ + 101011 rt:5 ra:5 d1:16 \ +!constraints { $ra != 0 && $ra != 1 && $ra != 13 && \ + $d0 <= 65535 && $d1 <= 32767 } \ +!memory { reg_plus_imm($ra, ($d0 << 16) | $d1); } + # format:XX3 book:I page:827 v3.01 xvbf16ger2 Prefixed Masked VSX Vector bfloat16 GER (rank-2 update) PMXVBF16GER2 PPC64LE 000001 11 1001 00 0 0 pmsk:2 000000 xmks:4 ymsk:4 \ 111011 at:3 00 a:5 b:5 00110011 ax:1 bx:1 0 @@ -1670,6 +1684,20 @@ PRTYD PPC64LE 011111 rs:5 ra:5 0000000101110100 \ PRTYW PPC64LE 011111 rs:5 ra:5 0000000100110100 \ !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; } +# format:8LS:D book:I page:646 v3.1B pstxsd Prefixed Store VSX Scalar Doubleword +PSTXSD PPC64LE 000001 00000 0 00 d0:18 \ + 101110 rs:5 ra:5 d1:16 \ +!constraints { $ra != 0 && $ra != 1 && $ra != 13 && \ + $d0 <= 65535 && $d1 <= 32767 } \ +!memory { reg_plus_imm($ra, ($d0 << 16) | $d1); } + +# format:8LS:D book:I page:650 v3.1B pstxssp Prefixed Store VSX Scalar Single-Precision +PSTXSSP PPC64LE 000001 00000 0 00 d0:18 \ + 101111 rs:5 ra:5 d1:16 \ +!constraints { $ra != 0 && $ra != 1 && $ra != 13 && \ + $d0 <= 65535 && $d1 <= 32767 } \ +!memory { reg_plus_imm($ra, ($d0 << 16) | $d1); } + # format:MDS book:I page:103 PPC SR rldcl Rotate Left Dword then Clear Left RLDCL PPC64LE 011110 rs:5 ra:5 rb:5 mb:6 10000 \ !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && $rb != 13; }