Handling extraneous commas (SystemVerilog)

[the-moog]

Existing code, which synthesises and simulates fine in Xilinx and Synopsys toolchains fails with hdlConverter.

The issue is extraneous commas in module parameter definitions and module instance signal connections.

This can be caused by `ifdefs removing parameters and are unused in a particular build.

e.g.
module X (input a, input b,); // Fails
module X (input a, input b); // Works

Similarly

X instX (.x(a), .y(b),); //Fails
X instX (.x(a), .y(b)); //Works

[Thomasb81]

What you request is non conform to verilog and systemVerilog standard.

I cannot confirm your claim see my log produced by Cadence, Mentor/Siemens and Synopsys.
dc_shell.log
xrun.log
questa.log

None of them consider this file has a valid syntax.

my test.sv file:

module test (input a, input b,);
endmodule

If that's due to preprocessor result better for you to include this trailing comma in the macro directive body in order to produce legal verilog or systemVerilog code.