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Atualizando casca do Hazard 3
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‎rtl/Hazard3.sv‎

Lines changed: 119 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -137,60 +137,104 @@ Controller #(
137137

138138
// Core space
139139

140+
// AHB - Instruction bus
141+
logic [31:0] haddr;
142+
logic hwrite;
143+
logic [2:0] hsize;
144+
logic [2:0] hburst;
145+
logic hmastlock;
146+
logic [3:0] hprot;
147+
logic [1:0] htrans;
148+
logic [31:0] hwdata;
149+
logic [31:0] hrdata;
150+
logic hready;
151+
logic hresp;
152+
153+
ahb_to_wishbone #( // bus adapter
154+
.ADDR_WIDTH(32),
155+
.DATA_WIDTH(32)
156+
) ahb2wb_inst (
157+
// Clock & Reset
158+
.HCLK (clk_core),
159+
.HRESETn (~rst_core),
160+
161+
// AHB interface
162+
.HADDR (haddr),
163+
.HTRANS (htrans),
164+
.HWRITE (hwrite),
165+
.HSIZE (hsize),
166+
.HBURST (hburst),
167+
.HPROT (hprot),
168+
.HLOCK (hmastlock),
169+
.HWDATA (hwdata),
170+
.HREADY (hready),
171+
.HRDATA (hrdata),
172+
.HREADYOUT (hready), // normalmente igual a HREADY em designs simples
173+
.HRESP (hresp),
174+
175+
// Wishbone interface
176+
.wb_cyc (core_cyc),
177+
.wb_stb (core_stb),
178+
.wb_we (core_we),
179+
.wb_adr (core_addr),
180+
.wb_dat_w (core_data_out),
181+
.wb_dat_r (core_data_in),
182+
.wb_ack (core_ack)
183+
);
184+
140185
hazard3_cpu_1port #(
141186
// These must have the values given here for you to end up with a useful SoC:
142-
.RESET_VECTOR (32'h0000_0040),
143-
.MTVEC_INIT (32'h0000_0000),
144-
.CSR_M_MANDATORY (1),
145-
.CSR_M_TRAP (1),
146-
.DEBUG_SUPPORT (1),
147-
.NUM_IRQS (1),
148-
.RESET_REGFILE (0),
187+
.RESET_VECTOR (32'h0000_0000),
188+
.MTVEC_INIT (32'h0000_0000),
189+
.CSR_M_MANDATORY (1),
190+
.CSR_M_TRAP (1),
191+
.DEBUG_SUPPORT (1),
192+
.NUM_IRQS (1),
193+
.RESET_REGFILE (0),
149194
// Can be overridden from the defaults in hazard3_config.vh during
150195
// instantiation of example_soc():
151-
.EXTENSION_A (EXTENSION_A),
152-
.EXTENSION_C (EXTENSION_C),
153-
.EXTENSION_M (EXTENSION_M),
154-
.EXTENSION_ZBA (EXTENSION_ZBA),
155-
.EXTENSION_ZBB (EXTENSION_ZBB),
156-
.EXTENSION_ZBC (EXTENSION_ZBC),
157-
.EXTENSION_ZBS (EXTENSION_ZBS),
158-
.EXTENSION_ZBKB (EXTENSION_ZBKB),
159-
.EXTENSION_ZIFENCEI (EXTENSION_ZIFENCEI),
160-
.EXTENSION_XH3BEXTM (EXTENSION_XH3BEXTM),
161-
.EXTENSION_XH3IRQ (EXTENSION_XH3IRQ),
162-
.EXTENSION_XH3PMPM (EXTENSION_XH3PMPM),
163-
.EXTENSION_XH3POWER (EXTENSION_XH3POWER),
164-
.CSR_COUNTER (CSR_COUNTER),
165-
.U_MODE (U_MODE),
166-
.PMP_REGIONS (PMP_REGIONS),
167-
.PMP_GRAIN (PMP_GRAIN),
168-
.PMP_HARDWIRED (PMP_HARDWIRED),
169-
.PMP_HARDWIRED_ADDR (PMP_HARDWIRED_ADDR),
170-
.PMP_HARDWIRED_CFG (PMP_HARDWIRED_CFG),
171-
.MVENDORID_VAL (MVENDORID_VAL),
172-
.BREAKPOINT_TRIGGERS (BREAKPOINT_TRIGGERS),
173-
.IRQ_PRIORITY_BITS (IRQ_PRIORITY_BITS),
174-
.MIMPID_VAL (MIMPID_VAL),
175-
.MHARTID_VAL (MHARTID_VAL),
176-
.REDUCED_BYPASS (REDUCED_BYPASS),
177-
.MULDIV_UNROLL (MULDIV_UNROLL),
178-
.MUL_FAST (MUL_FAST),
179-
.MUL_FASTER (MUL_FASTER),
180-
.MULH_FAST (MULH_FAST),
181-
.FAST_BRANCHCMP (FAST_BRANCHCMP),
182-
.BRANCH_PREDICTOR (BRANCH_PREDICTOR),
183-
.MTVEC_WMASK (MTVEC_WMASK)
196+
.EXTENSION_A (1),
197+
.EXTENSION_C (1),
198+
.EXTENSION_M (1),
199+
.EXTENSION_ZBA (1),
200+
.EXTENSION_ZBB (1),
201+
.EXTENSION_ZBC (1),
202+
.EXTENSION_ZBS (1),
203+
.EXTENSION_ZBKB (1),
204+
.EXTENSION_ZIFENCEI (1),
205+
.EXTENSION_XH3BEXTM (1),
206+
.EXTENSION_XH3IRQ (1),
207+
.EXTENSION_XH3PMPM (1),
208+
.EXTENSION_XH3POWER (1),
209+
.CSR_COUNTER (0),
210+
.U_MODE (0),
211+
.PMP_REGIONS (0),
212+
.PMP_GRAIN (0),
213+
.PMP_HARDWIRED (0),
214+
.PMP_HARDWIRED_ADDR (0),
215+
.PMP_HARDWIRED_CFG (0),
216+
.MVENDORID_VAL (0),
217+
.BREAKPOINT_TRIGGERS (0),
218+
.IRQ_PRIORITY_BITS (0),
219+
.MIMPID_VAL (0),
220+
.MHARTID_VAL (0),
221+
.REDUCED_BYPASS (0),
222+
.MULDIV_UNROLL (1),
223+
.MUL_FAST (0),
224+
.MUL_FASTER (1),
225+
.MULH_FAST (1),
226+
.FAST_BRANCHCMP (1),
227+
.BRANCH_PREDICTOR (1)
184228
) cpu (
185-
.clk (clk),
186-
.clk_always_on (clk),
187-
.rst_n (rst_n_cpu),
229+
.clk (clk_core),
230+
.clk_always_on (clk_core),
231+
.rst_n (~rst_core),
188232

189-
.pwrup_req (pwrup_req),
190-
.pwrup_ack (pwrup_req), // Tied back
191-
.clk_en (/* unused */),
192-
.unblock_out (unblock_out),
193-
.unblock_in (unblock_out), // Tied back
233+
.pwrup_req (),
234+
.pwrup_ack (1), // Tied back
235+
.clk_en (),
236+
.unblock_out (),
237+
.unblock_in (1), // Tied back
194238

195239
.haddr (proc_haddr),
196240
.hwrite (proc_hwrite),
@@ -206,35 +250,35 @@ hazard3_cpu_1port #(
206250
.hwdata (proc_hwdata),
207251
.hrdata (proc_hrdata),
208252

209-
.dbg_req_halt (hart_req_halt),
210-
.dbg_req_halt_on_reset (hart_req_halt_on_reset),
211-
.dbg_req_resume (hart_req_resume),
212-
.dbg_halted (hart_halted),
213-
.dbg_running (hart_running),
214-
215-
.dbg_data0_rdata (hart_data0_rdata),
216-
.dbg_data0_wdata (hart_data0_wdata),
217-
.dbg_data0_wen (hart_data0_wen),
218-
219-
.dbg_instr_data (hart_instr_data),
220-
.dbg_instr_data_vld (hart_instr_data_vld),
221-
.dbg_instr_data_rdy (hart_instr_data_rdy),
222-
.dbg_instr_caught_exception (hart_instr_caught_exception),
223-
.dbg_instr_caught_ebreak (hart_instr_caught_ebreak),
224-
225-
.dbg_sbus_addr (sbus_addr),
226-
.dbg_sbus_write (sbus_write),
227-
.dbg_sbus_size (sbus_size),
228-
.dbg_sbus_vld (sbus_vld),
229-
.dbg_sbus_rdy (sbus_rdy),
230-
.dbg_sbus_err (sbus_err),
231-
.dbg_sbus_wdata (sbus_wdata),
232-
.dbg_sbus_rdata (sbus_rdata),
233-
234-
.irq (uart_irq),
253+
.dbg_req_halt (0),
254+
.dbg_req_halt_on_reset (0),
255+
.dbg_req_resume (0),
256+
.dbg_halted (),
257+
.dbg_running (),
258+
259+
.dbg_data0_rdata (0),
260+
.dbg_data0_wdata (),
261+
.dbg_data0_wen (),
262+
263+
.dbg_instr_data (0),
264+
.dbg_instr_data_vld (0),
265+
.dbg_instr_data_rdy (),
266+
.dbg_instr_caught_exception (),
267+
.dbg_instr_caught_ebreak (),
268+
269+
.dbg_sbus_addr (0),
270+
.dbg_sbus_write (0),
271+
.dbg_sbus_size (0),
272+
.dbg_sbus_vld (0),
273+
.dbg_sbus_rdy (),
274+
.dbg_sbus_err (),
275+
.dbg_sbus_wdata (0),
276+
.dbg_sbus_rdata (),
277+
278+
.irq (0),
235279

236280
.soft_irq (1'b0),
237-
.timer_irq (timer_irq)
281+
.timer_irq (0)
238282
);
239283

240284
endmodule

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