Atualizando cascas

Author: JN513

.gitignore

@@ -179,3 +179,5 @@ rename.py
 march.py
 experiment/
 repositories.txt
+work-obj93.cf
+rvx.txt

config/cv32e40p.json

@@ -3,6 +3,9 @@
     "folder": "cv32e40p",
     "sim_files": [],
     "files": [
+        "rtl/include/cv32e40p_apu_core_pkg.sv",
+        "rtl/include/cv32e40p_fpu_pkg.sv",
+        "rtl/include/cv32e40p_pkg.sv",
         "rtl/cv32e40p_aligner.sv",
         "rtl/cv32e40p_alu.sv",
         "rtl/cv32e40p_alu_div.sv",
@@ -15,7 +18,6 @@
         "rtl/cv32e40p_ex_stage.sv",
         "rtl/cv32e40p_ff_one.sv",
         "rtl/cv32e40p_fifo.sv",
-        "rtl/cv32e40p_fp_wrapper.sv",
         "rtl/cv32e40p_hwloop_regs.sv",
         "rtl/cv32e40p_id_stage.sv",
         "rtl/cv32e40p_if_stage.sv",
@@ -27,15 +29,14 @@
         "rtl/cv32e40p_prefetch_buffer.sv",
         "rtl/cv32e40p_prefetch_controller.sv",
         "rtl/cv32e40p_register_file_ff.sv",
-        "rtl/cv32e40p_register_file_latch.sv",
         "rtl/cv32e40p_sleep_unit.sv",
         "rtl/cv32e40p_top.sv"
     ],
     "include_dirs": [
         "rtl/include/"
     ],
     "repository": "https://github.com/openhwgroup/cv32e40p",
-    "top_module": "",
+    "top_module": "cv32e40p_core",
     "extra_flags": [],
     "language_version": "2012",
     "march": "rv32i",

config/cv32e41p.json

@@ -14,12 +14,10 @@
         "example_tb/core/include/perturbation_pkg.sv"
     ],
     "files": [
-        "bhv/cv32e41p_apu_tracer.sv",
-        "bhv/cv32e41p_core_log.sv",
-        "bhv/cv32e41p_sim_clock_gate.sv",
-        "bhv/cv32e41p_tracer.sv",
-        "bhv/cv32e41p_wrapper.sv",
-        "bhv/include/cv32e41p_tracer_pkg.sv",
+
+        "rtl/include/cv32e41p_apu_core_pkg.sv",
+        "rtl/include/cv32e41p_fpu_pkg.sv",
+        "rtl/include/cv32e41p_pkg.sv",
         "rtl/cv32e41p_aligner.sv",
         "rtl/cv32e41p_alu.sv",
         "rtl/cv32e41p_alu_div.sv",
@@ -43,11 +41,7 @@
         "rtl/cv32e41p_prefetch_controller.sv",
         "rtl/cv32e41p_register_file_ff.sv",
         "rtl/cv32e41p_register_file_latch.sv",
-        "rtl/cv32e41p_sleep_unit.sv",
-        "rtl/include/cv32e41p_apu_core_pkg.sv",
-        "rtl/include/cv32e41p_fpu_pkg.sv",
-        "rtl/include/cv32e41p_pkg.sv",
-        "sva/cv32e41p_prefetch_controller_sva.sv"
+        "rtl/cv32e41p_sleep_unit.sv"
     ],
     "include_dirs": [],
     "repository": "https://github.com/openhwgroup/cv32e41p",

config/kronos.json

@@ -3,6 +3,7 @@
     "folder": "kronos",
     "sim_files": [],
     "files": [
+        "rtl/core/kronos_types.sv",
         "rtl/core/kronos_EX.sv",
         "rtl/core/kronos_ID.sv",
         "rtl/core/kronos_IF.sv",
@@ -14,8 +15,7 @@
         "rtl/core/kronos_counter64.sv",
         "rtl/core/kronos_csr.sv",
         "rtl/core/kronos_hcu.sv",
-        "rtl/core/kronos_lsu.sv",
-        "rtl/core/kronos_types.sv"
+        "rtl/core/kronos_lsu.sv"
     ],
     "include_dirs": [],
     "repository": "https://github.com/SonalPinto/kronos",

config/leaf.json

@@ -30,11 +30,10 @@
         "uart/tbs/uart_tb.vhdl"
     ],
     "files": [
+        "cpu/rtl/core_pkg.vhdl",
         "cpu/rtl/alu.vhdl",
         "cpu/rtl/alu_ctrl.vhdl",
         "cpu/rtl/br_detector.vhdl",
-        "cpu/rtl/core.vhdl",
-        "cpu/rtl/core_pkg.vhdl",
         "cpu/rtl/csrs.vhdl",
         "cpu/rtl/ex_block.vhdl",
         "cpu/rtl/id_block.vhdl",
@@ -47,25 +46,11 @@
         "cpu/rtl/main_ctrl.vhdl",
         "cpu/rtl/reg_file.vhdl",
         "cpu/rtl/wb_ctrl.vhdl",
-        "soc/rtl/debug_reg.vhdl",
-        "soc/rtl/leaf_soc.vhdl",
-        "soc/rtl/leaf_soc_pkg.vhdl",
-        "soc/rtl/ram.vhdl",
-        "soc/rtl/rom.vhdl",
-        "soc/rtl/soc_syscon.vhdl",
-        "uart/rtl/down_counter.vhdl",
-        "uart/rtl/fifo.vhdl",
-        "uart/rtl/piso.vhdl",
-        "uart/rtl/sipo.vhdl",
-        "uart/rtl/uart.vhdl",
-        "uart/rtl/uart_pkg.vhdl",
-        "uart/rtl/uart_rx.vhdl",
-        "uart/rtl/uart_tx.vhdl",
-        "uart/rtl/uart_wbsl.vhdl"
+        "cpu/rtl/core.vhdl"
     ],
     "include_dirs": [],
     "repository": "https://github.com/daniel-santos-7/leaf",
-    "top_module": "",
+    "top_module": "core",
     "extra_flags": [],
     "language_version": "08",
     "march": "rv32i",

config/microrv32.json

@@ -11,5 +11,6 @@
     "extra_flags": [],
     "language_version": "2005",
     "march": "rv32i",
-    "two_memory": false
+    "two_memory": false,
+    "pre_script": "cd microrv32 && sbt run"
 }

config/riscado-v.json

@@ -10,7 +10,9 @@
         "riscv.v",
         "load_store.v"
     ],
-    "include_dirs": [],
+    "include_dirs": [
+        "./"
+    ],
     "repository": "https://github.com/zxmarcos/riscado-v",
     "top_module": "RISCV",
     "extra_flags": [],

core/fpga.py

@@ -227,7 +227,7 @@ def make_build_file(config: dict, board: str, toolchain_path: str) -> str:
         for i in config['files']:
             is_sv_file = i.endswith('.sv')
             prefix = get_prefix(
-                board, vhdl=i.endswith('.vhd'), sverilog=is_sv_file
+                board, vhdl=i.endswith('.vhd') or i.endswith('.vhdl'), sverilog=is_sv_file
             )
             exist_sv_file = exist_sv_file or is_sv_file
             if is_sv_file and board in YOSYS_BOARDS:

internal/memory.hex

@@ -0,0 +1,5 @@
+00500593
+00000013
+00000013
+00000013
+02b02e23

internal/memory.sv

@@ -0,0 +1,41 @@
+module Memory #(
+    parameter MEMORY_FILE = "",
+    parameter MEMORY_SIZE = 4096
+)(
+    input  logic        clk,
+
+    input  logic        cyc_i,      // Indica uma transação ativa
+    input  logic        stb_i,      // Indica uma solicitação ativa
+    input  logic        we_i,       // 1 = Write, 0 = Read
+
+    input  logic [31:0] addr_i,     // Endereço
+    input  logic [31:0] data_i,     // Dados de entrada (para escrita)
+    output logic [31:0] data_o,     // Dados de saída (para leitura)
+
+    output logic        ack_o       // Confirmação da transação (agora assíncrona)
+);
+
+    localparam BIT_INDEX = $clog2(MEMORY_SIZE) - 1'b1;
+    logic [31:0] memory [(MEMORY_SIZE/4)-1:0];
+
+    // Inicialização da memória com arquivo, se fornecido
+    initial begin
+        if (MEMORY_FILE != "") begin
+            $readmemh(MEMORY_FILE, memory);
+        end
+    end
+
+    // Leitura assíncrona
+    assign data_o = (cyc_i && stb_i && !we_i) ? memory[addr_i[BIT_INDEX:2]] : 32'd0;
+
+    // Resposta assíncrona de ACK (igual ao antigo `response`)
+    assign ack_o = cyc_i && stb_i;  
+
+    // Escrita síncrona
+    always_ff @(posedge clk) begin
+        if (cyc_i && stb_i && we_i) begin
+            memory[addr_i[BIT_INDEX:2]] <= data_i;
+        end
+    end
+
+endmodule