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Merge pull request #12 from LSC-Unicamp/reestruturando_projeto
Corrigindo sinais da memoria de dados
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‎rtl/axi4_to_wishbone.sv‎

Lines changed: 168 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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module axi4_to_wishbone_simple #(
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parameter ADDR_WIDTH = 32,
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parameter DATA_WIDTH = 32,
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parameter ID_WIDTH = 4
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)(
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input logic clk,
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input logic rst_n,
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// AXI Write Address Channel
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input logic [ID_WIDTH-1:0] S_AXI_AWID,
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input logic [ADDR_WIDTH-1:0] S_AXI_AWADDR,
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input logic S_AXI_AWVALID,
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output logic S_AXI_AWREADY,
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// AXI Write Data Channel
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input logic [DATA_WIDTH-1:0] S_AXI_WDATA,
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input logic [(DATA_WIDTH/8)-1:0] S_AXI_WSTRB,
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input logic S_AXI_WVALID,
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output logic S_AXI_WREADY,
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// AXI Write Response Channel
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output logic [ID_WIDTH-1:0] S_AXI_BID,
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output logic [1:0] S_AXI_BRESP,
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output logic S_AXI_BVALID,
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input logic S_AXI_BREADY,
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// AXI Read Address Channel
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input logic [ID_WIDTH-1:0] S_AXI_ARID,
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input logic [ADDR_WIDTH-1:0] S_AXI_ARADDR,
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input logic S_AXI_ARVALID,
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output logic S_AXI_ARREADY,
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// AXI Read Data Channel
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output logic [ID_WIDTH-1:0] S_AXI_RID,
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output logic [DATA_WIDTH-1:0] S_AXI_RDATA,
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output logic [1:0] S_AXI_RRESP,
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output logic S_AXI_RVALID,
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input logic S_AXI_RREADY,
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// Wishbone Interface
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output logic WB_CYC,
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output logic WB_STB,
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output logic WB_WE,
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output logic [ADDR_WIDTH-1:0] WB_ADDR,
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output logic [DATA_WIDTH-1:0] WB_WDATA,
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output logic [(DATA_WIDTH/8)-1:0] WB_SEL,
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input logic [DATA_WIDTH-1:0] WB_RDATA,
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input logic WB_ACK
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);
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// Estados
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typedef enum logic [2:0] {
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IDLE,
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WB_WRITE,
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WB_WRITE_RESP,
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WB_READ,
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WB_READ_RESP
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} state_t;
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state_t state, next_state;
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// Registradores internos
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logic [ADDR_WIDTH-1:0] addr_reg;
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logic [DATA_WIDTH-1:0] wdata_reg;
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logic [(DATA_WIDTH/8)-1:0] wstrb_reg;
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logic [ID_WIDTH-1:0] id_reg;
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logic is_write;
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// FSM principal
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= IDLE;
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end else begin
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state <= next_state;
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end
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end
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always_comb begin
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// Defaults
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S_AXI_AWREADY = 0;
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S_AXI_WREADY = 0;
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S_AXI_BVALID = 0;
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S_AXI_BRESP = 2'b00;
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S_AXI_BID = id_reg;
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S_AXI_ARREADY = 0;
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S_AXI_RVALID = 0;
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S_AXI_RRESP = 2'b00;
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S_AXI_RDATA = WB_RDATA;
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S_AXI_RID = id_reg;
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WB_CYC = 0;
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WB_STB = 0;
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WB_WE = 0;
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WB_ADDR = addr_reg;
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WB_WDATA = wdata_reg;
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WB_SEL = wstrb_reg;
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next_state = state;
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case (state)
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IDLE: begin
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if (S_AXI_AWVALID && S_AXI_WVALID) begin
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next_state = WB_WRITE;
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end else if (S_AXI_ARVALID) begin
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next_state = WB_READ;
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end
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end
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WB_WRITE: begin
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WB_CYC = 1;
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WB_STB = 1;
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WB_WE = 1;
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if (WB_ACK) begin
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next_state = WB_WRITE_RESP;
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end
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end
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WB_WRITE_RESP: begin
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S_AXI_BVALID = 1;
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if (S_AXI_BREADY) begin
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next_state = IDLE;
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end
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end
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WB_READ: begin
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WB_CYC = 1;
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WB_STB = 1;
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if (WB_ACK) begin
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next_state = WB_READ_RESP;
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end
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end
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WB_READ_RESP: begin
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S_AXI_RVALID = 1;
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if (S_AXI_RREADY) begin
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next_state = IDLE;
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end
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end
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endcase
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end
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// Captura de endereço/dados
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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addr_reg <= 0;
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wdata_reg <= 0;
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wstrb_reg <= 0;
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id_reg <= 0;
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end else begin
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if (state == IDLE) begin
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if (S_AXI_AWVALID && S_AXI_WVALID) begin
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addr_reg <= S_AXI_AWADDR;
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wdata_reg <= S_AXI_WDATA;
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wstrb_reg <= S_AXI_WSTRB;
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id_reg <= S_AXI_AWID;
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S_AXI_AWREADY <= 1;
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S_AXI_WREADY <= 1;
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end else if (S_AXI_ARVALID) begin
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addr_reg <= S_AXI_ARADDR;
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id_reg <= S_AXI_ARID;
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S_AXI_ARREADY <= 1;
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end
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end
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end
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end
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endmodule

‎rtl/controller.sv‎

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,11 @@ always_ff @(posedge clk ) begin
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finish_execution <= 1'b0;
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else begin
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if(bus_mode) begin
163-
if(core_addr_i[5:0] == end_position[5:0])
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if(core_addr_i[5:0] == end_position[5:0]
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`ifdef ENABLE_SECOND_MEMORY
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|| data_mem_addr_i[5:0] == end_position[5:0]
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`endif
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)
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finish_execution <= 1'b1;
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end else begin
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if(core_addr_i == end_position
@@ -285,15 +289,15 @@ Memory #(
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) Core_Data_Memory (
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.clk (clk),
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288-
.cyc_i (data_memory_cyc_i),
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.stb_i (data_memory_stb_i),
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.we_i (data_memory_we_i),
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.cyc_i (data_memory_cyc),
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.stb_i (data_memory_stb),
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.we_i (data_memory_we),
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.addr_i (data_memory_addr_i),
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.data_i (data_memory_data_i),
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.data_o (data_memory_data_o),
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.addr_i (data_memory_address),
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.data_i (data_memory_write_data),
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.data_o (data_memory_read_data),
295299

296-
.ack_o (data_memory_ack_o)
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.ack_o (data_memory_ack)
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);
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`endif
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