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JN513JN513
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Merge pull request #11 from LSC-Unicamp/reestruturando_projeto
Reestruturando projeto
2 parents 3edd873 + 26cea03 commit 0ef3017

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‎.github/workflows/clk_divider.yml‎

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name: ClkDivider Test
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on: [push, pull_request]
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jobs:
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test:
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runs-on: ubuntu-latest
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steps:
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- name: Checkout do código
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uses: actions/checkout@v4
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- name: Instalar Icarus Verilog (iverilog)
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run: sudo apt update && sudo apt install -y iverilog
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- name: Criar diretório de build
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run: mkdir -p build
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- name: Compilar o testbench
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run: iverilog -o build/ClkDivider_tb -s ClkDivider_tb -g2005-sv -Irtl/core testbenchs/clk_divider_tb.sv rtl/clk_divider.sv
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- name: Executar o testbench
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run: vvp build/ClkDivider_tb
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- name: Salvar VCD como artefato
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uses: actions/upload-artifact@v4
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with:
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name: fifo_waveform
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path: build/ClkDivider_tb.vcd

‎.github/workflows/fifo.yml‎

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name: FIFO Test
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on: [push, pull_request]
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jobs:
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test:
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runs-on: ubuntu-latest
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steps:
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- name: Checkout do código
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uses: actions/checkout@v4
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- name: Instalar Icarus Verilog (iverilog)
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run: sudo apt update && sudo apt install -y iverilog
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- name: Criar diretório de build
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run: mkdir -p build
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- name: Compilar o testbench
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run: iverilog -o build/fifo_tb -s fifo_tb -g2005-sv -Irtl/core testbenchs/fifo_tb.sv rtl/fifo.sv
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- name: Executar o testbench
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run: vvp build/fifo_tb
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- name: Salvar VCD como artefato
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uses: actions/upload-artifact@v4
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with:
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name: fifo_waveform
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path: build/fifo_tb.vcd

‎.gitignore‎

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webtalk*.jou
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fpga/digilent_arty/usage_statistics_webtalk.xml
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fpga/digilent_arty/usage_statistics_webtalk.html
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fpga/nexys4_ddr/clockInfo.txt
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fpga/nexys4_ddr/usage_statistics_webtalk.html
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fpga/nexys4_ddr/usage_statistics_webtalk.xml

‎.gitmodules‎

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url = https://github.com/Unicamp-Odhin/SPI-Slave
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[submodule "modules/UART"]
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path = modules/UART
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url = https://github.com/ben-marshall/uart
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[submodule "modules/Risco-5"]
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path = modules/Risco-5
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url = https://github.com/JN513/Risco-5
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url = https://github.com/ben-marshall/uart

‎Risco-5‎

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This file was deleted.

‎examples/Grande-Risco-5.sv‎

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module top (
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input logic clk,
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input logic CPU_RESETN,
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input logic rx,
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output logic tx,
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input logic mosi,
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output logic miso,
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input logic sck,
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input logic cs
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);
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logic clk_o;
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logic clk_core, rst_core;
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// Fios do barramento entre Controller e Processor
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logic core_cyc;
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logic core_stb;
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logic core_we;
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logic [31:0] core_addr;
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logic [31:0] core_data_out;
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logic [31:0] core_data_in;
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logic core_ack;
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Controller #(
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.CLK_FREQ (50000000),
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.BIT_RATE (BIT_RATE),
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.PAYLOAD_BITS (8),
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.BUFFER_SIZE (8),
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.PULSE_CONTROL_BITS (32),
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.BUS_WIDTH (32),
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.WORD_SIZE_BY (4),
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.ID (32'h7700006A),
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.RESET_CLK_CYCLES (20),
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.MEMORY_FILE (""),
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.MEMORY_SIZE (4096)
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) u_Controller (
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.clk (clk),
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.rst_n (CPU_RESETN),
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// SPI signals
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.sck_i (sck),
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.cs_i (cs),
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.mosi_i (mosi),
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.miso_o (miso),
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// SPI callback signals
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.rw_i (),
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.intr_o (),
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// UART signals
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.rx (rx),
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.tx (tx),
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// Clock, reset, and bus signals
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.clk_core_o (clk_core),
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.rst_core_o (rst_core),
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// Barramento padrão (não AXI4-Lite)
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.core_cyc_i (core_cyc),
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.core_stb_i (core_stb),
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.core_we_i (core_we),
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.core_addr_i (core_addr),
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.core_data_i (core_data_out),
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.core_data_o (core_data_in),
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.core_ack_o (core_ack)
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);
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Grande_Risco5 #(
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.BOOT_ADDRESS (32'h00000000),
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.I_CACHE_SIZE (256),
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.D_CACHE_SIZE (256),
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.DATA_WIDTH (32),
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.ADDR_WIDTH (32),
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.BRANCH_PREDICTION_SIZE (128)
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) Processor (
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.clk (clk_core),
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.rst_n (~rst_core),
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.halt (1'b0),
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.cyc_o (core_cyc),
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.stb_o (core_stb),
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.we_o (core_we),
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.addr_o (core_addr),
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.data_o (core_data_out),
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.ack_i (core_ack),
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.data_i (core_data_in),
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.interruption (1'b0)
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);
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always_ff @(posedge clk) begin : CLOCK_DIVIDER
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if (!CPU_RESETN) begin
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clk_o <= 1'b0;
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end else begin
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clk_o <= ~clk_o;
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end
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end
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endmodule

‎fpga/nexys4_ddr/.gitignore‎

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digilent_arty.ip_user_files/
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.Xil/
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report/
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vivado_*.backup.*
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vivado_*.backup.*
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reports

‎fpga/nexys4_ddr/Makefile‎

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ifndef VIVADO_PATH
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VIVADO=vivado
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else
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VIVADO=$(VIVADO_PATH)/vivado
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endif
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all: ./build/out.bit
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./build/out.bit: buildFolder
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vivado -mode batch -nolog -nojournal -source run.tcl
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$(VIVADO) -mode batch -nolog -nojournal -source run.tcl
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buildFolder:
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mkdir -p build
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mkdir -p reports
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clean:
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rm -rf build
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rm clockInfo.txt
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rm -rf clockInfo.txt
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rm -rf .Xil
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rm -rf reports
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flash:
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load:
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openFPGALoader -b nexys_a7_100 ./build/out.bit
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run_all: ./build/out.bit flash
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flash:
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openFPGALoader -b nexys_a7_100 -f ./build/out.bit
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run_all: ./build/out.bit load

‎fpga/nexys4_ddr/main.sv‎

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module top (
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input logic clk,
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input logic CPU_RESETN,
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input logic rx,
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output logic tx,
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output logic [15:0]LED,
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input logic mosi,
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output logic miso,
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input logic sck,
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input logic cs,
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input logic [15:0] SW,
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output logic [3:0] VGA_R,
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output logic [3:0] VGA_G,
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output logic [3:0] VGA_B,
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output logic VGA_HS,
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output logic VGA_VS,
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output logic M_CLK, // Clock do microfone
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output logic M_LRSEL, // Left/Right Select (Escolha do canal)
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input logic M_DATA // Dados do microfone
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);
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logic clk_o;
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logic clk_core, rst_core;
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Controller #(
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.CLK_FREQ (50000000),
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.BIT_RATE (115200),
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.PAYLOAD_BITS (8),
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.BUFFER_SIZE (8),
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.PULSE_CONTROL_BITS (32),
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.BUS_WIDTH (32),
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.WORD_SIZE_BY (4),
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.ID (32'h7700006A),
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.RESET_CLK_CYCLES (20),
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.MEMORY_FILE (""),
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.MEMORY_SIZE (4096)
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) u_Controller (
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.clk (clk_o),
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.rst_n (CPU_RESETN),
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// SPI signals
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.sck_i (sck),
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.cs_i (cs),
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.mosi_i (mosi),
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.miso_o (miso),
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// SPI callback signals
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.rw_i (),
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.intr_o (),
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// UART signals
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.rx (rx),
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.tx (tx),
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// Clock, reset, and bus signals
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.clk_core_o (clk_core),
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.rst_core_o (rst_core),
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// Barramento padrão (não AXI4-Lite)
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.core_cyc_i (),
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.core_stb_i (),
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.core_we_i (),
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.core_addr_i (),
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.core_data_i (),
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.core_data_o (),
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.core_ack_o ()
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`ifdef ENABLE_SECOND_MEMORY
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,
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// Segunda memória - memória de dados
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.data_mem_cyc_i (data_mem_cyc_i),
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.data_mem_stb_i (data_mem_stb_i),
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.data_mem_we_i (data_mem_we_i),
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.data_mem_addr_i (data_mem_addr_i),
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.data_mem_data_i (data_mem_data_i),
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.data_mem_data_o (data_mem_data_o),
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.data_mem_ack_o (data_mem_ack_o)
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`endif
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);
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always_ff @(posedge clk) begin
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if(!CPU_RESETN)
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clk_o <= 1'b0;
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else
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clk_o <= ~clk_o;
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end
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endmodule

‎fpga/nexys4_ddr/main.v‎

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