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Adicionando IP para memoria
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‎fpga/opensourceSDRLabKintex7/Makefile‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,11 +32,11 @@ clean:
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3333
load:
3434
@echo "Loading the bitstream onto the FPGA..."
35-
./openFPGALoader -b opensourceSDRLabKintex7 $(BISTREAM)
35+
openFPGALoader -b opensourceSDRLabKintex7 $(BISTREAM)
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flash:
3838
@echo "Flashing the bitstream onto the FPGA..."
39-
./openFPGALoader -b opensourceSDRLabKintex7 -f $(BISTREAM)
39+
openFPGALoader -b opensourceSDRLabKintex7 -f $(BISTREAM)
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remote:
4242
@echo "Uploading the bitstream to a remote server..."

‎fpga/opensourceSDRLabKintex7/generate_ip.tcl‎

Lines changed: 167 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,167 @@
1+
create_project -force ip_project ./ip_project -part xc7k325tffg676-2
2+
3+
create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name mig_7series_0 -dir ./ip
4+
5+
set_property -dict [list \
6+
CONFIG.ARESETN.INSERT_VIP {0} \
7+
CONFIG.BOARD_MIG_PARAM {Custom} \
8+
CONFIG.C0_ARESETN.INSERT_VIP {0} \
9+
CONFIG.C0_CLOCK.INSERT_VIP {0} \
10+
CONFIG.C0_DDR2_RESET.INSERT_VIP {0} \
11+
CONFIG.C0_DDR3_RESET.INSERT_VIP {0} \
12+
CONFIG.C0_LPDDR2_RESET.INSERT_VIP {0} \
13+
CONFIG.C0_MMCM_CLKOUT0.INSERT_VIP {0} \
14+
CONFIG.C0_MMCM_CLKOUT1.INSERT_VIP {0} \
15+
CONFIG.C0_MMCM_CLKOUT2.INSERT_VIP {0} \
16+
CONFIG.C0_MMCM_CLKOUT3.INSERT_VIP {0} \
17+
CONFIG.C0_MMCM_CLKOUT4.INSERT_VIP {0} \
18+
CONFIG.C0_QDRIIP_RESET.INSERT_VIP {0} \
19+
CONFIG.C0_RESET.INSERT_VIP {0} \
20+
CONFIG.C0_RLDIII_RESET.INSERT_VIP {0} \
21+
CONFIG.C0_RLDII_RESET.INSERT_VIP {0} \
22+
CONFIG.C0_SYS_CLK_I.INSERT_VIP {0} \
23+
CONFIG.C1_ARESETN.INSERT_VIP {0} \
24+
CONFIG.C1_CLOCK.INSERT_VIP {0} \
25+
CONFIG.C1_DDR2_RESET.INSERT_VIP {0} \
26+
CONFIG.C1_DDR3_RESET.INSERT_VIP {0} \
27+
CONFIG.C1_LPDDR2_RESET.INSERT_VIP {0} \
28+
CONFIG.C1_MMCM_CLKOUT0.INSERT_VIP {0} \
29+
CONFIG.C1_MMCM_CLKOUT1.INSERT_VIP {0} \
30+
CONFIG.C1_MMCM_CLKOUT2.INSERT_VIP {0} \
31+
CONFIG.C1_MMCM_CLKOUT3.INSERT_VIP {0} \
32+
CONFIG.C1_MMCM_CLKOUT4.INSERT_VIP {0} \
33+
CONFIG.C1_QDRIIP_RESET.INSERT_VIP {0} \
34+
CONFIG.C1_RESET.INSERT_VIP {0} \
35+
CONFIG.C1_RLDIII_RESET.INSERT_VIP {0} \
36+
CONFIG.C1_RLDII_RESET.INSERT_VIP {0} \
37+
CONFIG.C1_SYS_CLK_I.INSERT_VIP {0} \
38+
CONFIG.C2_ARESETN.INSERT_VIP {0} \
39+
CONFIG.C2_CLOCK.INSERT_VIP {0} \
40+
CONFIG.C2_DDR2_RESET.INSERT_VIP {0} \
41+
CONFIG.C2_DDR3_RESET.INSERT_VIP {0} \
42+
CONFIG.C2_LPDDR2_RESET.INSERT_VIP {0} \
43+
CONFIG.C2_MMCM_CLKOUT0.INSERT_VIP {0} \
44+
CONFIG.C2_MMCM_CLKOUT1.INSERT_VIP {0} \
45+
CONFIG.C2_MMCM_CLKOUT2.INSERT_VIP {0} \
46+
CONFIG.C2_MMCM_CLKOUT3.INSERT_VIP {0} \
47+
CONFIG.C2_MMCM_CLKOUT4.INSERT_VIP {0} \
48+
CONFIG.C2_QDRIIP_RESET.INSERT_VIP {0} \
49+
CONFIG.C2_RESET.INSERT_VIP {0} \
50+
CONFIG.C2_RLDIII_RESET.INSERT_VIP {0} \
51+
CONFIG.C2_RLDII_RESET.INSERT_VIP {0} \
52+
CONFIG.C2_SYS_CLK_I.INSERT_VIP {0} \
53+
CONFIG.C3_ARESETN.INSERT_VIP {0} \
54+
CONFIG.C3_CLOCK.INSERT_VIP {0} \
55+
CONFIG.C3_DDR2_RESET.INSERT_VIP {0} \
56+
CONFIG.C3_DDR3_RESET.INSERT_VIP {0} \
57+
CONFIG.C3_LPDDR2_RESET.INSERT_VIP {0} \
58+
CONFIG.C3_MMCM_CLKOUT0.INSERT_VIP {0} \
59+
CONFIG.C3_MMCM_CLKOUT1.INSERT_VIP {0} \
60+
CONFIG.C3_MMCM_CLKOUT2.INSERT_VIP {0} \
61+
CONFIG.C3_MMCM_CLKOUT3.INSERT_VIP {0} \
62+
CONFIG.C3_MMCM_CLKOUT4.INSERT_VIP {0} \
63+
CONFIG.C3_QDRIIP_RESET.INSERT_VIP {0} \
64+
CONFIG.C3_RESET.INSERT_VIP {0} \
65+
CONFIG.C3_RLDIII_RESET.INSERT_VIP {0} \
66+
CONFIG.C3_RLDII_RESET.INSERT_VIP {0} \
67+
CONFIG.C3_SYS_CLK_I.INSERT_VIP {0} \
68+
CONFIG.C4_ARESETN.INSERT_VIP {0} \
69+
CONFIG.C4_CLOCK.INSERT_VIP {0} \
70+
CONFIG.C4_DDR2_RESET.INSERT_VIP {0} \
71+
CONFIG.C4_DDR3_RESET.INSERT_VIP {0} \
72+
CONFIG.C4_LPDDR2_RESET.INSERT_VIP {0} \
73+
CONFIG.C4_MMCM_CLKOUT0.INSERT_VIP {0} \
74+
CONFIG.C4_MMCM_CLKOUT1.INSERT_VIP {0} \
75+
CONFIG.C4_MMCM_CLKOUT2.INSERT_VIP {0} \
76+
CONFIG.C4_MMCM_CLKOUT3.INSERT_VIP {0} \
77+
CONFIG.C4_MMCM_CLKOUT4.INSERT_VIP {0} \
78+
CONFIG.C4_QDRIIP_RESET.INSERT_VIP {0} \
79+
CONFIG.C4_RESET.INSERT_VIP {0} \
80+
CONFIG.C4_RLDIII_RESET.INSERT_VIP {0} \
81+
CONFIG.C4_RLDII_RESET.INSERT_VIP {0} \
82+
CONFIG.C4_SYS_CLK_I.INSERT_VIP {0} \
83+
CONFIG.C5_ARESETN.INSERT_VIP {0} \
84+
CONFIG.C5_CLOCK.INSERT_VIP {0} \
85+
CONFIG.C5_DDR2_RESET.INSERT_VIP {0} \
86+
CONFIG.C5_DDR3_RESET.INSERT_VIP {0} \
87+
CONFIG.C5_LPDDR2_RESET.INSERT_VIP {0} \
88+
CONFIG.C5_MMCM_CLKOUT0.INSERT_VIP {0} \
89+
CONFIG.C5_MMCM_CLKOUT1.INSERT_VIP {0} \
90+
CONFIG.C5_MMCM_CLKOUT2.INSERT_VIP {0} \
91+
CONFIG.C5_MMCM_CLKOUT3.INSERT_VIP {0} \
92+
CONFIG.C5_MMCM_CLKOUT4.INSERT_VIP {0} \
93+
CONFIG.C5_QDRIIP_RESET.INSERT_VIP {0} \
94+
CONFIG.C5_RESET.INSERT_VIP {0} \
95+
CONFIG.C5_RLDIII_RESET.INSERT_VIP {0} \
96+
CONFIG.C5_RLDII_RESET.INSERT_VIP {0} \
97+
CONFIG.C5_SYS_CLK_I.INSERT_VIP {0} \
98+
CONFIG.C6_ARESETN.INSERT_VIP {0} \
99+
CONFIG.C6_CLOCK.INSERT_VIP {0} \
100+
CONFIG.C6_DDR2_RESET.INSERT_VIP {0} \
101+
CONFIG.C6_DDR3_RESET.INSERT_VIP {0} \
102+
CONFIG.C6_LPDDR2_RESET.INSERT_VIP {0} \
103+
CONFIG.C6_MMCM_CLKOUT0.INSERT_VIP {0} \
104+
CONFIG.C6_MMCM_CLKOUT1.INSERT_VIP {0} \
105+
CONFIG.C6_MMCM_CLKOUT2.INSERT_VIP {0} \
106+
CONFIG.C6_MMCM_CLKOUT3.INSERT_VIP {0} \
107+
CONFIG.C6_MMCM_CLKOUT4.INSERT_VIP {0} \
108+
CONFIG.C6_QDRIIP_RESET.INSERT_VIP {0} \
109+
CONFIG.C6_RESET.INSERT_VIP {0} \
110+
CONFIG.C6_RLDIII_RESET.INSERT_VIP {0} \
111+
CONFIG.C6_RLDII_RESET.INSERT_VIP {0} \
112+
CONFIG.C6_SYS_CLK_I.INSERT_VIP {0} \
113+
CONFIG.C7_ARESETN.INSERT_VIP {0} \
114+
CONFIG.C7_CLOCK.INSERT_VIP {0} \
115+
CONFIG.C7_DDR2_RESET.INSERT_VIP {0} \
116+
CONFIG.C7_DDR3_RESET.INSERT_VIP {0} \
117+
CONFIG.C7_LPDDR2_RESET.INSERT_VIP {0} \
118+
CONFIG.C7_MMCM_CLKOUT0.INSERT_VIP {0} \
119+
CONFIG.C7_MMCM_CLKOUT1.INSERT_VIP {0} \
120+
CONFIG.C7_MMCM_CLKOUT2.INSERT_VIP {0} \
121+
CONFIG.C7_MMCM_CLKOUT3.INSERT_VIP {0} \
122+
CONFIG.C7_MMCM_CLKOUT4.INSERT_VIP {0} \
123+
CONFIG.C7_QDRIIP_RESET.INSERT_VIP {0} \
124+
CONFIG.C7_RESET.INSERT_VIP {0} \
125+
CONFIG.C7_RLDIII_RESET.INSERT_VIP {0} \
126+
CONFIG.C7_RLDII_RESET.INSERT_VIP {0} \
127+
CONFIG.C7_SYS_CLK_I.INSERT_VIP {0} \
128+
CONFIG.CLK_REF_I.INSERT_VIP {0} \
129+
CONFIG.CLOCK.INSERT_VIP {0} \
130+
CONFIG.DDR2_RESET.INSERT_VIP {0} \
131+
CONFIG.DDR3_RESET.INSERT_VIP {0} \
132+
CONFIG.LPDDR2_RESET.INSERT_VIP {0} \
133+
CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \
134+
CONFIG.MMCM_CLKOUT0.INSERT_VIP {0} \
135+
CONFIG.MMCM_CLKOUT1.INSERT_VIP {0} \
136+
CONFIG.MMCM_CLKOUT2.INSERT_VIP {0} \
137+
CONFIG.MMCM_CLKOUT3.INSERT_VIP {0} \
138+
CONFIG.MMCM_CLKOUT4.INSERT_VIP {0} \
139+
CONFIG.QDRIIP_RESET.INSERT_VIP {0} \
140+
CONFIG.RESET.INSERT_VIP {0} \
141+
CONFIG.RESET_BOARD_INTERFACE {Custom} \
142+
CONFIG.RLDIII_RESET.INSERT_VIP {0} \
143+
CONFIG.RLDII_RESET.INSERT_VIP {0} \
144+
CONFIG.S0_AXI.INSERT_VIP {0} \
145+
CONFIG.S0_AXI_CTRL.INSERT_VIP {0} \
146+
CONFIG.S1_AXI.INSERT_VIP {0} \
147+
CONFIG.S1_AXI_CTRL.INSERT_VIP {0} \
148+
CONFIG.S2_AXI.INSERT_VIP {0} \
149+
CONFIG.S2_AXI_CTRL.INSERT_VIP {0} \
150+
CONFIG.S3_AXI.INSERT_VIP {0} \
151+
CONFIG.S3_AXI_CTRL.INSERT_VIP {0} \
152+
CONFIG.S4_AXI.INSERT_VIP {0} \
153+
CONFIG.S4_AXI_CTRL.INSERT_VIP {0} \
154+
CONFIG.S5_AXI.INSERT_VIP {0} \
155+
CONFIG.S5_AXI_CTRL.INSERT_VIP {0} \
156+
CONFIG.S6_AXI.INSERT_VIP {0} \
157+
CONFIG.S6_AXI_CTRL.INSERT_VIP {0} \
158+
CONFIG.S7_AXI.INSERT_VIP {0} \
159+
CONFIG.S7_AXI_CTRL.INSERT_VIP {0} \
160+
CONFIG.SYSTEM_RESET.INSERT_VIP {0} \
161+
CONFIG.SYS_CLK_I.INSERT_VIP {0} \
162+
CONFIG.S_AXI.INSERT_VIP {0} \
163+
CONFIG.S_AXI_CTRL.INSERT_VIP {0} \
164+
CONFIG.XML_INPUT_FILE {/eda/projetos/Risco-5-family/Grande-Risco-5/fpga/opensourceSDRLabKintex7/mig_a.prj} \
165+
] [get_ips mig_7series_0]
166+
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generate_target all [get_ips mig_7series_0]

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