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JN513JN513
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Alterando frequencia de operação
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-109
lines changed

25 files changed

+2729
-109
lines changed

‎fpga/artyA7_100t/generate_ip.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@ create_project -force ip_project ./ip_project -part xc7a100tcsg324-1
44
# Cria o IP "clk_wiz_0" do tipo "clk_wiz" na pasta "ip/"
55
create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_0 -dir ./ip
66

7-
# Configurações básicas do IP (exemplo: entrada de 100 MHz, saída de 50 MHz)
7+
# Configurações básicas do IP (exemplo: entrada de 100 MHz, saída de 65 MHz)
88
set_property -dict [list \
99
CONFIG.PRIM_IN_FREQ {100.0} \
10-
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} \
10+
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {65} \
1111
CONFIG.USE_PHASE_ALIGNMENT {true} \
1212
CONFIG.RESET_TYPE {ACTIVE_LOW} \
1313
CONFIG.USE_RESET {true} \

‎fpga/artyA7_100t/ip/clk_wiz_0/clk_wiz_0.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@
5353
// Output Output Phase Duty Cycle Pk-to-Pk Phase
5454
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
5555
//----------------------------------------------------------------------------
56-
// clk_out1__50.00000______0.000______50.0______151.636_____98.575
56+
// clk_out1__65.00000______0.000______50.0______254.866____297.890
5757
//
5858
//----------------------------------------------------------------------------
5959
// Input Clock Freq (MHz) Input Jitter (UI)

‎fpga/artyA7_100t/ip/clk_wiz_0/clk_wiz_0.xci‎

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@
8484
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
8585
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
8686
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
87-
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "50", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
87+
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "65", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
8888
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
8989
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
9090
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -154,9 +154,9 @@
154154
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
155155
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
156156
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
157-
"MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
157+
"MMCM_DIVCLK_DIVIDE": [ { "value": "5", "resolve_type": "user", "format": "long", "usage": "all" } ],
158158
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
159-
"MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
159+
"MMCM_CLKFBOUT_MULT_F": [ { "value": "50.375", "resolve_type": "user", "format": "float", "usage": "all" } ],
160160
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
161161
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
162162
"MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -167,7 +167,7 @@
167167
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
168168
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
169169
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
170-
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "20.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
170+
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "15.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
171171
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
172172
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
173173
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
@@ -245,8 +245,8 @@
245245
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
246246
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
247247
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
248-
"CLKOUT1_JITTER": [ { "value": "151.636", "resolve_type": "user", "format": "float", "usage": "all" } ],
249-
"CLKOUT1_PHASE_ERROR": [ { "value": "98.575", "resolve_type": "user", "format": "float", "usage": "all" } ],
248+
"CLKOUT1_JITTER": [ { "value": "254.866", "resolve_type": "user", "format": "float", "usage": "all" } ],
249+
"CLKOUT1_PHASE_ERROR": [ { "value": "297.890", "resolve_type": "user", "format": "float", "usage": "all" } ],
250250
"CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
251251
"CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
252252
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
@@ -338,14 +338,14 @@
338338
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
339339
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
340340
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
341-
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__50.00000______0.000______50.0______151.636_____98.575", "resolve_type": "generated", "usage": "all" } ],
341+
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__65.00000______0.000______50.0______254.866____297.890", "resolve_type": "generated", "usage": "all" } ],
342342
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
343343
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
344344
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
345345
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
346346
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
347347
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
348-
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "50", "resolve_type": "generated", "format": "float", "usage": "all" } ],
348+
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "65", "resolve_type": "generated", "format": "float", "usage": "all" } ],
349349
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
350350
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
351351
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
@@ -366,7 +366,7 @@
366366
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
367367
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
368368
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
369-
"C_CLKOUT1_OUT_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
369+
"C_CLKOUT1_OUT_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
370370
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
371371
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
372372
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
@@ -398,17 +398,17 @@
398398
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
399399
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
400400
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
401-
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
401+
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "50.375", "resolve_type": "generated", "format": "float", "usage": "all" } ],
402402
"C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
403403
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
404404
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
405405
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
406406
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
407-
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
407+
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
408408
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
409409
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
410410
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
411-
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "20.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
411+
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "15.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
412412
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
413413
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
414414
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
@@ -540,12 +540,12 @@
540540
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
541541
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
542542
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
543-
"C_DIVIDE2_AUTO": [ { "value": "0.05", "resolve_type": "generated", "usage": "all" } ],
544-
"C_DIVIDE3_AUTO": [ { "value": "0.05", "resolve_type": "generated", "usage": "all" } ],
545-
"C_DIVIDE4_AUTO": [ { "value": "0.05", "resolve_type": "generated", "usage": "all" } ],
546-
"C_DIVIDE5_AUTO": [ { "value": "0.05", "resolve_type": "generated", "usage": "all" } ],
547-
"C_DIVIDE6_AUTO": [ { "value": "0.05", "resolve_type": "generated", "usage": "all" } ],
548-
"C_DIVIDE7_AUTO": [ { "value": "0.05", "resolve_type": "generated", "usage": "all" } ],
543+
"C_DIVIDE2_AUTO": [ { "value": "0.06451612903225806", "resolve_type": "generated", "usage": "all" } ],
544+
"C_DIVIDE3_AUTO": [ { "value": "0.06451612903225806", "resolve_type": "generated", "usage": "all" } ],
545+
"C_DIVIDE4_AUTO": [ { "value": "0.06451612903225806", "resolve_type": "generated", "usage": "all" } ],
546+
"C_DIVIDE5_AUTO": [ { "value": "0.06451612903225806", "resolve_type": "generated", "usage": "all" } ],
547+
"C_DIVIDE6_AUTO": [ { "value": "0.06451612903225806", "resolve_type": "generated", "usage": "all" } ],
548+
"C_DIVIDE7_AUTO": [ { "value": "0.06451612903225806", "resolve_type": "generated", "usage": "all" } ],
549549
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
550550
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
551551
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
@@ -566,7 +566,7 @@
566566
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
567567
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
568568
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
569-
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "50.00000", "resolve_type": "generated", "usage": "all" } ],
569+
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "65.00000", "resolve_type": "generated", "usage": "all" } ],
570570
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
571571
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
572572
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],

‎fpga/artyA7_100t/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@
5353
// Output Output Phase Duty Cycle Pk-to-Pk Phase
5454
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
5555
//----------------------------------------------------------------------------
56-
// clk_out1__50.00000______0.000______50.0______151.636_____98.575
56+
// clk_out1__65.00000______0.000______50.0______254.866____297.890
5757
//
5858
//----------------------------------------------------------------------------
5959
// Input Clock Freq (MHz) Input Jitter (UI)
@@ -124,11 +124,11 @@ wire clk_in2_clk_wiz_0;
124124
.CLKOUT4_CASCADE ("FALSE"),
125125
.COMPENSATION ("ZHOLD"),
126126
.STARTUP_WAIT ("FALSE"),
127-
.DIVCLK_DIVIDE (1),
128-
.CLKFBOUT_MULT_F (10.000),
127+
.DIVCLK_DIVIDE (5),
128+
.CLKFBOUT_MULT_F (50.375),
129129
.CLKFBOUT_PHASE (0.000),
130130
.CLKFBOUT_USE_FINE_PS ("FALSE"),
131-
.CLKOUT0_DIVIDE_F (20.000),
131+
.CLKOUT0_DIVIDE_F (15.500),
132132
.CLKOUT0_PHASE (0.000),
133133
.CLKOUT0_DUTY_CYCLE (0.500),
134134
.CLKOUT0_USE_FINE_PS ("FALSE"),

‎fpga/artyA7_100t/main.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ clk_wiz_0 clk_wiz_inst (
2121

2222

2323
Grande_Risco_5_SOC #(
24-
.CLOCK_FREQ (50_000_000),
24+
.CLOCK_FREQ (65_000_000),
2525
.BAUD_RATE (115200),
2626
.MEMORY_SIZE (4096),
2727
.MEMORY_FILE ("../../verification_tests/memory/led_test2.hex"),

‎fpga/nexys4_ddr/generate_ip.tcl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@ create_project -force ip_project ./ip_project -part xc7a100tcsg324-1
44
# Cria o IP "clk_wiz_0" do tipo "clk_wiz" na pasta "ip/"
55
create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name clk_wiz_0 -dir ./ip
66

7-
# Configurações básicas do IP (exemplo: entrada de 100 MHz, saída de 50 MHz)
7+
# Configurações básicas do IP (exemplo: entrada de 100 MHz, saída de 65 MHz)
88
set_property -dict [list \
99
CONFIG.PRIM_IN_FREQ {100.0} \
10-
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50} \
10+
CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {65} \
1111
CONFIG.USE_PHASE_ALIGNMENT {true} \
1212
CONFIG.RESET_TYPE {ACTIVE_LOW} \
1313
CONFIG.USE_RESET {true} \

‎fpga/nexys4_ddr/ip/clk_wiz_0/clk_wiz_0.v‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@
5353
// Output Output Phase Duty Cycle Pk-to-Pk Phase
5454
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
5555
//----------------------------------------------------------------------------
56-
// clk_out1__50.00000______0.000______50.0______151.636_____98.575
56+
// clk_out1__65.00000______0.000______50.0______254.866____297.890
5757
//
5858
//----------------------------------------------------------------------------
5959
// Input Clock Freq (MHz) Input Jitter (UI)

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