UART Baudrate Spartan-6

[ryancor]

Hey! I was wondering if you could help me out with some issues I seem to be having with whats coming out of the TX line. So I'm following along for the FPGA-peripherals/uart-tx/examples/txstr/
and i got everything working but when i read the serial data, instead of "Hello!.." I get a bunch of garbage ascii. I'm assuming this could be because of the fact that your baudgen.vh file was generated for a 12Mhz clock.

I used your python script for what it shows my clock speed is at 50Mhz

python baudgen.py
`define B115200 434
`define B57600 868
`define B38400 1302
`define B19200 2604
`define B9600 5208
`define B4800 10417
`define B2400 20833
`define B1200 41667
`define B600 83333
`define B300 166667

But for some reason I'm still getting garbage ascii, with `define B115200 434 i am getting the correct amount of chars printed out in the terminal which is progress but I can't seem to figure out what else I'm doing wrong. I'm using the manual off here https://usermanual.wiki/Document/ax309xilinxspartan6developmentboardusersmanual.1355685398.pdf

RESET pin is at L3
TX pin at D12
CLK pin is at T8

AX309 equips a 50MHz OSC for system clock source. The oscillator output is connected to the FPGA's
global clock (GCLK Pin T8

Is it maybe something with my constraints file that I would need to add extra for the TX or CLK pin. Or something off with how the baud is being calculated?

Heres my ucf file

NET "clk" LOC = T8 | IOSTANDARD = LVCMOS33 | PERIOD = 50000 kHz;
#NET "clk" TNM_NET = "sys_clk_pin";
#TIMESPEC "TS_sys_clk_pin" = PERIOD "sys_clk_pin" 50000 kHz;

NET "rstn" LOC = L3 | IOSTANDARD = LVCMOS33;
NET "tx" LOC = D12 | IOSTANDARD = LVCMOS33 | DRIVE=8 | SLEW=FAST;

Thank you!