risc-v vector extensions

[sh-zheng]

Hello,
The spec of vector extension of risc-v will be frozen soon. Do we have any plan to support risc-v vector extension?

[stevengj]

No plans that I know of, but since FFTW already supports several SIMD instruction sets it shouldn't be hard to add another one if someone has access to hardware and a compiler…

[rdolbeau]

See https://github.com/rdolbeau/fftw3/tree/riscv-v for a prototype.

[Gandalfthegreybeard]

See https://github.com/rdolbeau/fftw3/tree/riscv-v for a prototype.

What version of the risc-v V spec does that use? From the timing, I'm guessing the 0.71 spec, which although having been encoded in the D1 chip, using the Xuantie C906 processor, has been revised fairly substantially into the 1.0 ratified spec available at https://github.com/riscv/riscv-v-spec

[nick-knight]

@stevengj Upstream QEMU and LLVM support RISC-V V-extension (ratified Nov. 2021). The C intrinsics API
https://github.com/riscv-non-isa/rvv-intrinsic-doc
is still churning, but there is general consensus on what needs to change, and work is underway.

[sh-zheng]

@nick-knight The pull request #279 has been raised. The codes are based on recent rvv intrinsic api and have been tested on qemu 7.0