POST#8 on Nexys Video – MicroBlaze in Reset / Dhrystone Performance Problem

[debbie0-0v1]

Thank you for the GitHub resources.

I'm currently working on POST#8 and have a question regarding Dhrystone performance.
I'm using the Nexys Video board.

While working on POST7 and POST8, I noticed that there is no "Skip Internal Test" option.
I modified the .xdc file (referring to the one for Nexys Video from GitHub), and followed your site's guidance. The Dhrystone performance I got is as follows:

Microseconds for one run through Dhrystone: 286.5121
Dhrystones per Second: 3490.2544
DMIPS/Sec: 1.9865
DMIPS/MHz: 0.0238
Compared to the results shown on your site, the performance is significantly lower 😢
Could it be because the Internal Test is still being included during the performance measurement?

Also, I'm wondering — if I use the example_demo/nexys_video setup, can I achieve the same performance results as yours?
If possible, I’d really appreciate it if you could share the steps or method to do that.

In addition, when I try to connect i_clk to sys_clock and i_rst to the reset pin in /example_demo/nexys_video/nexysvideo_ddr3.xdc, I get the following error in Vitis simulation:

Cannot reset MicroBlaze #0. Cannot stop MicroBlaze. MicroBlaze is held in reset

How can I successfully run POST#8 on the Nexys Video board?

[AngeloJacobo]

Hi @debbie0-0v1, sorry for late response. Would it be possible to send here the Vivado project? Or send me via email (jacobo.angeloECE@gmail.com). Please also let me know the Vivado version you are running on

[debbie0-0v1]

Hello! I’m currently using version 2023.2. I’ve tried using MIG7 and achieved a DMIPS/MHz of 0.3288. During this process, I confirmed that when executing VITIS, the address for MIG is automatically generated (excluding BRAM). However, when I tried using UberDDR3, the address was *not* automatically generated in VITIS. After several attempts, I noticed that increasing the Dhrystone loop constraint for UberDDR3 led to a higher DMIPS/MHz. Honestly, based on the results I’ve seen, it seems that UberDDR3 wasn’t properly recognized in my simulation... I suspect that the problem lies in my XDC file. Since the Nexys Video board doesn’t have a CS pin, I replaced it with the addr[14] pin instead... 😥 Also, I resolved an issue where the reset wasn’t being recognized correctly in version 2023.2. I tested both nexysvideo_wrapper.xsa and nexysvideo_v1_wrapper.xsa using VITIS, and I set the loop constant in VITIS to 480000. At first, the performance was very slow, so I tried increasing the cache length, which gave somewhat better performance. But after comparing it to MIG7, I realized something was wrong with my setup. The file is too large, so for now I’m sending the XDC file only. I’ll think about a way to send the rest. This is my first time working with SoCs, so I think I’m making a lot of mistakes. However, I’ve been studying hard by reading your POST, and it has been really helpful! I’m truly sorry to bother you, but I would be incredibly grateful if I could get some help from you!

On Fri, May 30, 2025 at 8:54 AM Angelo Jacobo ***@***.***> wrote: *AngeloJacobo* left a comment (AngeloJacobo/UberDDR3#33) <#33 (comment)> Hi @debbie0-0v1 <https://github.com/debbie0-0v1>, sorry for late response. Would it be possible to send here the Vivado project? Or send me via email ***@***.***). Please also let me know the Vivado version you are running on — Reply to this email directly, view it on GitHub <#33 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/BRSZY736BFRQPZMTH7IBFJ33A6M2NAVCNFSM6AAAAAB6CLVOX6VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDSMRQHAZTGNJQG4> . You are receiving this because you were mentioned.Message ID: ***@***.***>

#set_property -dict {PACKAGE_PIN R4 IOSTANDARD LVCMOS33} [get_ports sys_clock] #create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports sys_clock] #set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS15 } [get_ports { reset }] #set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS33} [get_ports tx] #set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports rx] set_property SLEW FAST [get_ports {ddr3_dq[0]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}] set_property PACKAGE_PIN G2 [get_ports {ddr3_dq[0]}] set_property SLEW FAST [get_ports {ddr3_dq[1]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}] set_property PACKAGE_PIN H4 [get_ports {ddr3_dq[1]}] set_property SLEW FAST [get_ports {ddr3_dq[2]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}] set_property PACKAGE_PIN H5 [get_ports {ddr3_dq[2]}] set_property SLEW FAST [get_ports {ddr3_dq[3]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}] set_property PACKAGE_PIN J1 [get_ports {ddr3_dq[3]}] set_property SLEW FAST [get_ports {ddr3_dq[4]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}] set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[4]}] set_property SLEW FAST [get_ports {ddr3_dq[5]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}] set_property PACKAGE_PIN H3 [get_ports {ddr3_dq[5]}] set_property SLEW FAST [get_ports {ddr3_dq[6]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}] set_property PACKAGE_PIN H2 [get_ports {ddr3_dq[6]}] set_property SLEW FAST [get_ports {ddr3_dq[7]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}] set_property PACKAGE_PIN J5 [get_ports {ddr3_dq[7]}] set_property SLEW FAST [get_ports {ddr3_dq[8]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}] set_property PACKAGE_PIN E3 [get_ports {ddr3_dq[8]}] set_property SLEW FAST [get_ports {ddr3_dq[9]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}] set_property PACKAGE_PIN B2 [get_ports {ddr3_dq[9]}] set_property SLEW FAST [get_ports {ddr3_dq[10]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}] set_property PACKAGE_PIN F3 [get_ports {ddr3_dq[10]}] set_property SLEW FAST [get_ports {ddr3_dq[11]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}] set_property PACKAGE_PIN D2 [get_ports {ddr3_dq[11]}] set_property SLEW FAST [get_ports {ddr3_dq[12]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}] set_property PACKAGE_PIN C2 [get_ports {ddr3_dq[12]}] set_property SLEW FAST [get_ports {ddr3_dq[13]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}] set_property PACKAGE_PIN A1 [get_ports {ddr3_dq[13]}] set_property SLEW FAST [get_ports {ddr3_dq[14]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}] set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[14]}] set_property SLEW FAST [get_ports {ddr3_dq[15]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}] set_property PACKAGE_PIN B1 [get_ports {ddr3_dq[15]}] #set_property SLEW FAST [get_ports {ddr3_addr[14]}] #set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}] #set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[14]}] set_property SLEW FAST [get_ports {ddr3_addr[13]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}] set_property PACKAGE_PIN P2 [get_ports {ddr3_addr[13]}] set_property SLEW FAST [get_ports {ddr3_addr[12]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}] set_property PACKAGE_PIN N4 [get_ports {ddr3_addr[12]}] set_property SLEW FAST [get_ports {ddr3_addr[11]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}] set_property PACKAGE_PIN N5 [get_ports {ddr3_addr[11]}] set_property SLEW FAST [get_ports {ddr3_addr[10]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}] set_property PACKAGE_PIN L5 [get_ports {ddr3_addr[10]}] set_property SLEW FAST [get_ports {ddr3_addr[9]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}] set_property PACKAGE_PIN R1 [get_ports {ddr3_addr[9]}] set_property SLEW FAST [get_ports {ddr3_addr[8]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}] set_property PACKAGE_PIN M6 [get_ports {ddr3_addr[8]}] set_property SLEW FAST [get_ports {ddr3_addr[7]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}] set_property PACKAGE_PIN N2 [get_ports {ddr3_addr[7]}] set_property SLEW FAST [get_ports {ddr3_addr[6]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}] set_property PACKAGE_PIN N3 [get_ports {ddr3_addr[6]}] set_property SLEW FAST [get_ports {ddr3_addr[5]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}] set_property PACKAGE_PIN P1 [get_ports {ddr3_addr[5]}] set_property SLEW FAST [get_ports {ddr3_addr[4]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}] set_property PACKAGE_PIN L6 [get_ports {ddr3_addr[4]}] set_property SLEW FAST [get_ports {ddr3_addr[3]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}] set_property PACKAGE_PIN M1 [get_ports {ddr3_addr[3]}] set_property SLEW FAST [get_ports {ddr3_addr[2]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}] set_property PACKAGE_PIN M3 [get_ports {ddr3_addr[2]}] set_property SLEW FAST [get_ports {ddr3_addr[1]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}] set_property PACKAGE_PIN M5 [get_ports {ddr3_addr[1]}] set_property SLEW FAST [get_ports {ddr3_addr[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}] set_property PACKAGE_PIN M2 [get_ports {ddr3_addr[0]}] set_property SLEW FAST [get_ports {ddr3_ba[2]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}] set_property PACKAGE_PIN L4 [get_ports {ddr3_ba[2]}] set_property SLEW FAST [get_ports {ddr3_ba[1]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}] set_property PACKAGE_PIN K6 [get_ports {ddr3_ba[1]}] set_property SLEW FAST [get_ports {ddr3_ba[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}] set_property PACKAGE_PIN L3 [get_ports {ddr3_ba[0]}] set_property SLEW FAST [get_ports ddr3_ras_n] set_property IOSTANDARD SSTL15 [get_ports ddr3_ras_n] set_property PACKAGE_PIN J4 [get_ports ddr3_ras_n] set_property SLEW FAST [get_ports ddr3_cas_n] set_property IOSTANDARD SSTL15 [get_ports ddr3_cas_n] set_property PACKAGE_PIN K3 [get_ports ddr3_cas_n] set_property SLEW FAST [get_ports ddr3_we_n] set_property IOSTANDARD SSTL15 [get_ports ddr3_we_n] set_property PACKAGE_PIN L1 [get_ports ddr3_we_n] set_property SLEW FAST [get_ports ddr3_reset_n] set_property IOSTANDARD LVCMOS15 [get_ports ddr3_reset_n] set_property PACKAGE_PIN G1 [get_ports ddr3_reset_n] set_property SLEW FAST [get_ports ddr3_cke] set_property IOSTANDARD SSTL15 [get_ports ddr3_cke] set_property PACKAGE_PIN J6 [get_ports ddr3_cke] set_property SLEW FAST [get_ports ddr3_odt] set_property IOSTANDARD SSTL15 [get_ports ddr3_odt] set_property PACKAGE_PIN K4 [get_ports ddr3_odt] set_property SLEW FAST [get_ports ddr3_cs_n] set_property IOSTANDARD SSTL15 [get_ports ddr3_cs_n] set_property PACKAGE_PIN P6 [get_ports ddr3_cs_n] set_property SLEW FAST [get_ports {ddr3_dm[0]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}] set_property PACKAGE_PIN G3 [get_ports {ddr3_dm[0]}] set_property SLEW FAST [get_ports {ddr3_dm[1]}] set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}] set_property PACKAGE_PIN F1 [get_ports {ddr3_dm[1]}] set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}] set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}] set_property PACKAGE_PIN K2 [get_ports {ddr3_dqs_p[0]}] set_property PACKAGE_PIN J2 [get_ports {ddr3_dqs_n[0]}] set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}] set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}] set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}] set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}] set_property PACKAGE_PIN E1 [get_ports {ddr3_dqs_p[1]}] set_property PACKAGE_PIN D1 [get_ports {ddr3_dqs_n[1]}] set_property SLEW FAST [get_ports ddr3_ck_p] set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr3_ck_p] set_property SLEW FAST [get_ports ddr3_ck_n] set_property IOSTANDARD DIFF_SSTL15 [get_ports ddr3_ck_n] set_property PACKAGE_PIN P5 [get_ports ddr3_ck_p] set_property PACKAGE_PIN P4 [get_ports ddr3_ck_n] set_property INTERNAL_VREF 0.75 [get_iobanks 35] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design]