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conform to the Power State Coordination Interface specification <aclass="reference internal" href="#document-references#psci" id="id1"><span>[PSCI]</span></a> and to
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the SMC Calling Convention <aclass="reference internal" href="#document-references#smccc" id="id2"><span>[SMCCC]</span></a>.</p>
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<p>Platforms without EL3 must implement PSCI and SMCCC at EL2 (leaving only EL1
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available to an operating system).</p>
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available to an operating system). <aclass="footnote-reference brackets" href="#conduitnote" id="id3" role="doc-noteref"><spanclass="fn-bracket">[</span>1<spanclass="fn-bracket">]</span></a></p>
<p>Refer to <aclass="reference internal" href="#document-references#smccc" id="id4"><span>[SMCCC]</span></a> § 2.5.3 Conduits for details on the conduit
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instructions (SMC & HVC) and their dependence on Exception Levels (EL3 &
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EL2).</p>
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</aside>
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</aside>
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<p>It is recommended that firmware implements PSCI version 1.0 or later
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<aclass="footnote-reference brackets" href="#pscinote" id="id3" role="doc-noteref"><spanclass="fn-bracket">[</span>1<spanclass="fn-bracket">]</span></a> and SMCCC version 1.1 or later <aclass="footnote-reference brackets" href="#smcccnote" id="id4" role="doc-noteref"><spanclass="fn-bracket">[</span>2<spanclass="fn-bracket">]</span></a>.</p>
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<aclass="footnote-reference brackets" href="#pscinote" id="id5" role="doc-noteref"><spanclass="fn-bracket">[</span>2<spanclass="fn-bracket">]</span></a> and SMCCC version 1.1 or later <aclass="footnote-reference brackets" href="#smcccnote" id="id6" role="doc-noteref"><spanclass="fn-bracket">[</span>3<spanclass="fn-bracket">]</span></a>.</p>
<h4><spanclass="section-number">3.2.2. </span>AArch64 Firmware Framework<aclass="headerlink" href="#aarch64-firmware-framework" title="Link to this heading">¶</a></h4>
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<p>On AArch64 platforms, when privileged or secure firmware implements the Firmware
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Framework for A-profile (FF-A), it must conform to the Arm Firmware Framework
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for Arm A-profile specification <aclass="reference internal" href="#document-references#ffa" id="id5"><span>[FFA]</span></a> and it must support at least one callee
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version compatible with caller version 1.2. <aclass="footnote-reference brackets" href="#ffanote" id="id6" role="doc-noteref"><spanclass="fn-bracket">[</span>3<spanclass="fn-bracket">]</span></a></p>
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for Arm A-profile specification <aclass="reference internal" href="#document-references#ffa" id="id7"><span>[FFA]</span></a> and it must support at least one callee
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version compatible with caller version 1.2. <aclass="footnote-reference brackets" href="#ffanote" id="id8" role="doc-noteref"><spanclass="fn-bracket">[</span>4<spanclass="fn-bracket">]</span></a></p>
<p>FF-A is an Arm software architecture describing interfaces that
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standardize communication between software images and firmware, in the Secure
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world and the Normal world.
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FF-A v1.2 introduced support for multiple services UUIDs in a partition,
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which eases services discovery, as well as the supporting
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<cite>FFA_MSG_SEND_DIRECT_REQ2</cite> ABI.
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As per the FF-A specification <aclass="reference internal" href="#document-references#ffa" id="id7"><span>[FFA]</span></a> § 13.2 FFA_VERSION, all callee versions
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As per the FF-A specification <aclass="reference internal" href="#document-references#ffa" id="id9"><span>[FFA]</span></a> § 13.2 FFA_VERSION, all callee versions
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1.x, with x >= 2, are compatible with caller versions 1.0 to 1.x, which
<h4><spanclass="section-number">3.2.3. </span>AArch64 Platform Fault Detection<aclass="headerlink" href="#aarch64-platform-fault-detection" title="Link to this heading">¶</a></h4>
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<p>On AArch64 platforms, when privileged or secure firmware implements the Platform
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Fault Detection Interface (PFDI), it must be compliant with the requirements
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defined in <aclass="reference internal" href="#document-references#pfdi" id="id8"><span>[PFDI]</span></a> § 5 Compliance Requirements, and it must support a version
defined in <aclass="reference internal" href="#document-references#pfdi" id="id10"><span>[PFDI]</span></a> § 5 Compliance Requirements, and it must support a version
<h4><spanclass="section-number">3.2.4. </span>AArch64 System Control and Management<aclass="headerlink" href="#aarch64-system-control-and-management" title="Link to this heading">¶</a></h4>
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<p>On AArch64 platforms, when the System Control and Management Interface (SCMI) is
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described in the ACPI table or the Devicetree, it must conform to the Arm System
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Control and Management Interface specification <aclass="reference internal" href="#document-references#scmi" id="id10"><span>[SCMI]</span></a> and the following
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implementation requirements take precedence. <aclass="footnote-reference brackets" href="#scminote" id="id11" role="doc-noteref"><spanclass="fn-bracket">[</span>5<spanclass="fn-bracket">]</span></a></p>
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Control and Management Interface specification <aclass="reference internal" href="#document-references#scmi" id="id12"><span>[SCMI]</span></a> and the following
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implementation requirements take precedence. <aclass="footnote-reference brackets" href="#scminote" id="id13" role="doc-noteref"><spanclass="fn-bracket">[</span>6<spanclass="fn-bracket">]</span></a></p>
<p>SCMI is a set of software interfaces defined by Arm, used for
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system management.
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It can be implemented by privileged or secure firmware, or by another
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processor.</p>
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</aside>
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</aside>
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<tableclass="docutils align-default" id="id16">
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<caption><spanclass="caption-number">Table 3.1 </span><spanclass="caption-text">SCMI Implementation Requirements</span><aclass="headerlink" href="#id16" title="Link to this table">¶</a></caption>
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<tableclass="docutils align-default" id="id18">
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<caption><spanclass="caption-number">Table 3.1 </span><spanclass="caption-text">SCMI Implementation Requirements</span><aclass="headerlink" href="#id18" title="Link to this table">¶</a></caption>
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<colgroup>
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<colstyle="width: 33.3%" />
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<colstyle="width: 33.3%" />
@@ -1480,7 +1488,7 @@ <h4><span class="section-number">3.2.4. </span>AArch64 System Control and Manage
<p>SCMI specification v3.2 introduced version negotiation,
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which eases agents and platforms interoperability, and this is therefore the
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recommended implementation.</p>
@@ -1539,10 +1547,10 @@ <h4><span class="section-number">3.2.4. </span>AArch64 System Control and Manage
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<h4><spanclass="section-number">3.2.5. </span>AArch64 Random Number Generator<aclass="headerlink" href="#aarch64-random-number-generator" title="Link to this heading">¶</a></h4>
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<p>On AArch64 platforms, if the platform has a hardware entropy source it is
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recommended that privileged or secure firmware implements the True Random Number
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Generator Firmware Interface version 1.0, as defined in <aclass="reference internal" href="#document-references#trng" id="id13"><span>[TRNG]</span></a>. <aclass="footnote-reference brackets" href="#trngnote" id="id14" role="doc-noteref"><spanclass="fn-bracket">[</span>7<spanclass="fn-bracket">]</span></a></p>
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Generator Firmware Interface version 1.0, as defined in <aclass="reference internal" href="#document-references#trng" id="id15"><span>[TRNG]</span></a>. <aclass="footnote-reference brackets" href="#trngnote" id="id16" role="doc-noteref"><spanclass="fn-bracket">[</span>8<spanclass="fn-bracket">]</span></a></p>
<h3><spanclass="section-number">3.3. </span>RISC-V Multiprocessor Startup Protocol<aclass="headerlink" href="#risc-v-multiprocessor-startup-protocol" title="Link to this heading">¶</a></h3>
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<p>The resident firmware in M mode or hypervisor running in HS mode must implement
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and conform to at least SBI <aclass="reference internal" href="#document-references#rvsbispc" id="id15"><span>[RVSBISPC]</span></a> v2.0 with at least these extensions:</p>
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and conform to at least SBI <aclass="reference internal" href="#document-references#rvsbispc" id="id17"><span>[RVSBISPC]</span></a> v2.0 with at least these extensions:</p>
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<ulclass="simple">
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<li><p>Base Extension</p></li>
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<li><p>HART State Management Extension (HSM)</p></li>
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