Is it possible to recover PortConnectionSyntax (or .name) from a PortConnection?

[hankhsu1996]

In the following SystemVerilog code:

module top_module;
  submodule inst(.submodule_clk(top_clk));
endmodule

From InstanceSymbol, I can access the resolved PortConnection for the submodule_clk port. However, I need to get back to the actual syntax (.submodule_clk part) so I can provide a definition location for that token.

But it seems conn.name is not preserved or available. Is there any way to recover the original PortConnectionSyntax or equivalent syntax node from the resolved PortConnection?

[MikePopoloski]

Hmm, I think you should be able to call getExpression(), get the syntax node from that (which should be the connection's ExpressionSyntax), and then walk up the syntax tree until you find the PortConnectionSyntax.

This probably won't work for implicit connections right now, since only the SourceRange is stored, but that could probably be fixed without too much work.

[hankhsu1996]

Thanks! That makes sense. Just to add, not just implicit connections. Explicit ones like .output() with empty parentheses also don't return an expression syntax to walk from.